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From: Alexandre Courbot <acourbot@nvidia.com>
To: Danilo Krummrich <dakr@kernel.org>,
	Alice Ryhl <aliceryhl@google.com>,
	 David Airlie <airlied@gmail.com>,
	Simona Vetter <simona@ffwll.ch>
Cc: John Hubbard <jhubbard@nvidia.com>,
	 Alistair Popple <apopple@nvidia.com>,
	Timur Tabi <ttabi@nvidia.com>,
	 Eliot Courtney <ecourtney@nvidia.com>,
	Zhi Wang <zhiw@nvidia.com>,
	 nova-gpu@lists.linux.dev, rust-for-linux@vger.kernel.org,
	 linux-kernel@vger.kernel.org,
	Alexandre Courbot <acourbot@nvidia.com>,
	 Daniel Almeida <daniel.almeida@collabora.com>,
	Gary Guo <gary@garyguo.net>
Subject: [PATCH v3 06/13] rust: io: register: implement Copy and Clone for RegisterArrayLoc
Date: Tue, 10 Nov 2026 19:20:55 +0900	[thread overview]
Message-ID: <20261110-r000-fw-v3-6-20d79ebb646f@nvidia.com> (raw)
In-Reply-To: <20261110-r000-fw-v3-0-20d79ebb646f@nvidia.com>

Register array locations are small values that are cheap to copy, but
obtaining one can fail. Making them implement `Copy` lets the same
location be checked once and used for several accesses.

Cc: Danilo Krummrich <dakr@kernel.org>
Cc: Alice Ryhl <aliceryhl@google.com>
Cc: Daniel Almeida <daniel.almeida@collabora.com>
Cc: Gary Guo <gary@garyguo.net>
Acked-by: Danilo Krummrich <dakr@kernel.org>
Reviewed-by: Eliot Courtney <ecourtney@nvidia.com>
Reviewed-by: Gary Guo <gary@garyguo.net>
Signed-off-by: Alexandre Courbot <acourbot@nvidia.com>
---
 rust/kernel/io/register.rs | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/rust/kernel/io/register.rs b/rust/kernel/io/register.rs
index b6513fa0f412..08129e20698d 100644
--- a/rust/kernel/io/register.rs
+++ b/rust/kernel/io/register.rs
@@ -194,6 +194,15 @@ pub fn try_new(idx: usize) -> Option<Self> {
     }
 }
 
+impl<T: RegisterArray> Clone for RegisterArrayLoc<T> {
+    #[inline]
+    fn clone(&self) -> Self {
+        *self
+    }
+}
+
+impl<T: RegisterArray> Copy for RegisterArrayLoc<T> {}
+
 impl<Base: ?Sized, T> IoLoc<Base, T> for RegisterArrayLoc<T>
 where
     T: RegisterArray<Base = Base>,

-- 
2.56.0


  parent reply	other threads:[~2026-11-10 10:21 UTC|newest]

Thread overview: 14+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-11-10 10:20 [PATCH v3 00/13] gpu: nova-core: generic bootloader and falcon DMA changes for r000 Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 01/13] gpu: nova-core: separate the generic falcon bootloader from FWSEC Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 02/13] gpu: nova-core: falcon: widen the IMEM PIO offset to 24 bits Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 03/13] gpu: nova-core: move the bootloader DMEM descriptor out of FWSEC Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 04/13] gpu: nova-core: run the generic bootloader from its own type Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 05/13] gpu: nova-core: place the generic bootloader at the top of IMEM Alexandre Courbot
2026-11-10 10:20 ` Alexandre Courbot [this message]
2026-11-10 10:20 ` [PATCH v3 07/13] gpu: nova-core: falcon: introduce and use with_fbif_transcfg Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 08/13] gpu: nova-core: falcon: rename the local variables of dma_wr() Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 09/13] gpu: nova-core: falcon: allow DMEM DMA transfers to request tagging Alexandre Courbot
2026-11-10 10:20 ` [PATCH v3 10/13] gpu: nova-core: falcon: allow DMA transfers to read from a framebuffer address Alexandre Courbot
2026-11-10 10:21 ` [PATCH v3 11/13] gpu: nova-core: falcon: use src_start as FB offset for all DMA transfers Alexandre Courbot
2026-11-10 10:21 ` [PATCH v3 12/13] gpu: nova-core: falcon: check the per-block DMA offsets for overflow Alexandre Courbot
2026-11-10 10:21 ` [PATCH v3 13/13] gpu: nova-core: falcon: program the FBIF_TRANSCFG register in dma_wr Alexandre Courbot

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