[PATCH 2/7] pinctrl: airoha: add per pin mode field mux

[John Crispin <john@phrozen.org>]

Newer Airoha SoCs select the function of a pin through a mode field in
a dedicated IOMUX block instead of through function specific bits in
the chip SCU. The AN7589 has a 4 bit field per pin, eight pins per 32
bit register. A group can then need one register write per pin, and
the two entry regmap[] of a function group cannot carry that.

Let a function group supply a pin_modes[] array, parallel to the pins
of the group. When it is set, set_mux writes each mode into the IOMUX
regmap and then applies the regmap[] entries of the group, so a group
can combine its pin modes with a register write in the GPIO block.

A SoC with an IOMUX describes it in its match data with struct
airoha_pinctrl_iomux, which holds the width of the mode field. Probe
then takes the regmap from the airoha,iomux phandle.

No functional change for the existing SoCs.

Signed-off-by: John Crispin <john@phrozen.org>
---
 drivers/pinctrl/airoha/airoha-common.h  | 14 ++++++++
 drivers/pinctrl/airoha/pinctrl-airoha.c | 48 +++++++++++++++++++++++++
 2 files changed, 62 insertions(+)

diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index 850e733db15a..7a0cb8924e71 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -49,6 +49,12 @@
 		.group_size = ARRAY_SIZE(table##_func_group),		\
 	}
 
+#define PINCTRL_MODE_FUNC_GROUP(id, table)				\
+	{								\
+		.name = id,						\
+		.pin_modes = table##_modes,				\
+	}
+
 #define PINCTRL_CONF_DESC(p, offset, mask)				\
 	{								\
 		.pin = p,						\
@@ -75,6 +81,7 @@ struct airoha_pinctrl_func_group {
 		u32 val;
 	} regmap[2];
 	int regmap_size;
+	const u8 *pin_modes;
 };
 
 struct airoha_pinctrl_func {
@@ -102,6 +109,10 @@ struct airoha_gpiochip_regs {
 
 extern const struct airoha_gpiochip_regs airoha_gpiochip_regs_64;
 
+struct airoha_pinctrl_iomux {
+	u8 mode_bits;
+};
+
 struct airoha_pinctrl_confs_info {
 	const struct airoha_pinctrl_conf *confs;
 	unsigned int num_confs;
@@ -126,6 +137,8 @@ struct airoha_pinctrl {
 	const struct airoha_pinctrl_confs_info *confs_info;
 
 	struct regmap *chip_scu;
+	struct regmap *iomux;
+	const struct airoha_pinctrl_iomux *iomux_info;
 	struct regmap *regmap;
 
 	struct gpio_chip gpiochip;
@@ -135,6 +148,7 @@ struct airoha_pinctrl {
 
 struct airoha_pinctrl_match_data {
 	const char *chip_scu_compatible;
+	const struct airoha_pinctrl_iomux *iomux_info;
 	const char *pinctrl_name;
 	struct module *pinctrl_owner;
 	const struct airoha_gpiochip_regs *gpio_regs;
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index b50108826d8d..f9ae4020b764 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -401,6 +401,35 @@ static int airoha_pinctrl_add_gpiochip(struct airoha_pinctrl *pinctrl,
 }
 
 /* pinmux callbacks */
+static int airoha_pinmux_set_pin_mode(struct airoha_pinctrl *pinctrl,
+				      unsigned int pin, u8 mode)
+{
+	unsigned int mode_bits = pinctrl->iomux_info->mode_bits;
+	unsigned int modes_per_reg = sizeof(u32) * BITS_PER_BYTE / mode_bits;
+	unsigned int shift = (pin % modes_per_reg) * mode_bits;
+	unsigned int reg = (pin / modes_per_reg) * sizeof(u32);
+
+	return regmap_update_bits(pinctrl->iomux, reg,
+				  GENMASK(mode_bits - 1, 0) << shift,
+				  mode << shift);
+}
+
+static int airoha_pinmux_set_pin_modes(struct airoha_pinctrl *pinctrl,
+				       const struct group_desc *grp,
+				       const u8 *modes)
+{
+	int i, err;
+
+	for (i = 0; i < grp->grp.npins; i++) {
+		err = airoha_pinmux_set_pin_mode(pinctrl, grp->grp.pins[i],
+						 modes[i]);
+		if (err)
+			return err;
+	}
+
+	return 0;
+}
+
 static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
 				 unsigned int selector,
 				 unsigned int group)
@@ -431,6 +460,15 @@ static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
 		if (strcmp(group->name, grp->grp.name))
 			continue;
 
+		if (group->pin_modes) {
+			int err;
+
+			err = airoha_pinmux_set_pin_modes(pinctrl, grp,
+							  group->pin_modes);
+			if (err)
+				return err;
+		}
+
 		for (j = 0; j < group->regmap_size; j++) {
 			switch (group->regmap[j].mux) {
 			case AIROHA_FUNC_PWM_EXT_MUX:
@@ -824,6 +862,16 @@ int airoha_pinctrl_probe(struct platform_device *pdev)
 
 	pinctrl->chip_scu = map;
 
+	if (data->iomux_info) {
+		map = syscon_regmap_lookup_by_phandle(dev->of_node,
+						      "airoha,iomux");
+		if (IS_ERR(map))
+			return PTR_ERR(map);
+
+		pinctrl->iomux = map;
+		pinctrl->iomux_info = data->iomux_info;
+	}
+
 	/* Init pinctrl desc struct */
 	pinctrl->desc.name = data->pinctrl_name;
 	pinctrl->desc.owner = data->pinctrl_owner;
-- 
2.34.1