From: John Crispin <john@phrozen.org>
To: Lorenzo Bianconi <lorenzo@kernel.org>, Lee Jones <lee@kernel.org>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Linus Walleij <linusw@kernel.org>,
Bartosz Golaszewski <brgl@kernel.org>
Cc: Ahmed Naseef <naseefkm@gmail.com>,
Benjamin Larsson <benjamin.larsson@genexis.eu>,
Christian Marangi <ansuelsmth@gmail.com>,
devicetree@vger.kernel.org, lei.dong@airoha.com,
Linqi.zhang@airoha.com, linux-gpio@vger.kernel.org,
linux-kernel@vger.kernel.org, linux-mediatek@lists.infradead.org,
mfd@lists.linux.dev,
Mikhail Kshevetskiy <mikhail.kshevetskiy@iopsys.eu>,
Rajeev.kumar@airoha.com, upstream@airoha.com,
Weifeng.xu@airoha.com, zhengping.zhang@airoha.com
Subject: [PATCH 4/7] pinctrl: airoha: mux a requested GPIO through the IOMUX
Date: Tue, 10 Nov 2026 18:39:38 +0100 [thread overview]
Message-ID: <20261110173941.301478-5-john@phrozen.org> (raw)
In-Reply-To: <20261110173941.301478-1-john@phrozen.org>
On a SoC with an IOMUX block every pin turns into a GPIO with one mode
value, mode 0 on the AN7589. Add that value to struct
airoha_pinctrl_iomux and write it when gpiolib requests a pin, so no
SoC needs a gpio function with one group per pin.
Without an IOMUX the callback does nothing, so the existing SoCs keep
their explicit gpio functions and their behavior.
Signed-off-by: John Crispin <john@phrozen.org>
---
drivers/pinctrl/airoha/airoha-common.h | 1 +
drivers/pinctrl/airoha/pinctrl-airoha.c | 14 ++++++++++++++
2 files changed, 15 insertions(+)
diff --git a/drivers/pinctrl/airoha/airoha-common.h b/drivers/pinctrl/airoha/airoha-common.h
index 7a0cb8924e71..adfce89493f0 100644
--- a/drivers/pinctrl/airoha/airoha-common.h
+++ b/drivers/pinctrl/airoha/airoha-common.h
@@ -111,6 +111,7 @@ extern const struct airoha_gpiochip_regs airoha_gpiochip_regs_64;
struct airoha_pinctrl_iomux {
u8 mode_bits;
+ u8 gpio_mode;
};
struct airoha_pinctrl_confs_info {
diff --git a/drivers/pinctrl/airoha/pinctrl-airoha.c b/drivers/pinctrl/airoha/pinctrl-airoha.c
index 9116d3ded258..a805f542bc7b 100644
--- a/drivers/pinctrl/airoha/pinctrl-airoha.c
+++ b/drivers/pinctrl/airoha/pinctrl-airoha.c
@@ -430,6 +430,19 @@ static int airoha_pinmux_set_pin_modes(struct airoha_pinctrl *pinctrl,
return 0;
}
+static int airoha_pinmux_gpio_request_enable(struct pinctrl_dev *pctrl_dev,
+ struct pinctrl_gpio_range *range,
+ unsigned int pin)
+{
+ struct airoha_pinctrl *pinctrl = pinctrl_dev_get_drvdata(pctrl_dev);
+
+ if (!pinctrl->iomux_info)
+ return 0;
+
+ return airoha_pinmux_set_pin_mode(pinctrl, pin,
+ pinctrl->iomux_info->gpio_mode);
+}
+
static int airoha_pinmux_set_mux(struct pinctrl_dev *pctrl_dev,
unsigned int selector,
unsigned int group)
@@ -510,6 +523,7 @@ static const struct pinmux_ops airoha_pmxops = {
.get_functions_count = pinmux_generic_get_function_count,
.get_function_name = pinmux_generic_get_function_name,
.get_function_groups = pinmux_generic_get_function_groups,
+ .gpio_request_enable = airoha_pinmux_gpio_request_enable,
.gpio_set_direction = airoha_pinmux_set_direction,
.set_mux = airoha_pinmux_set_mux,
.strict = true,
--
2.34.1
next prev parent reply other threads:[~2026-11-10 17:39 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 17:39 [PATCH 0/7] pinctrl: airoha: add AN7589 support John Crispin
2026-11-10 17:39 ` [PATCH 1/7] pinctrl: airoha: make gpio register layout per SoC John Crispin
2026-11-10 17:39 ` [PATCH 2/7] pinctrl: airoha: add per pin mode field mux John Crispin
2026-11-10 17:39 ` [PATCH 3/7] pinctrl: airoha: make the chip SCU optional John Crispin
2026-11-10 17:39 ` John Crispin [this message]
2026-11-10 17:39 ` [PATCH 5/7] dt-bindings: pinctrl: airoha: add AN7589 John Crispin
2026-11-10 18:27 ` Conor Dooley
2026-11-10 17:39 ` [PATCH 6/7] pinctrl: airoha: move the GPIO register offsets to the common header John Crispin
2026-11-10 17:39 ` [PATCH 7/7] pinctrl: airoha: add support of an7589 SoC John Crispin
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