[PATCH v2 0/6] riscv: hwprobe: do not report disabled extensions

[PATCH v2 0/6] riscv: hwprobe: do not report disabled extensions

[Radim Krčmář]

Hello,

hwprobe currently looks at the hart's ISA when it reports RISC-V
extensions, but some of these extensions might be present in hart's ISA,
yet still disabled on that hart.
This series improves the situation by only reporting extensions that the
hwprobe caller can actually use on all queried harts.

v1: https://lore.kernel.org/linux-riscv/20261006075303.205216-1-radim.krcmar@oss.qualcomm.com/
v2:
 * [4/6] Used pmlen helpers from v7.4-rc1 [Guodong]
 * (hopefully) improved commit messages
 * r-b

The series changed mainly in the commit messages.
A small semantic change in [4/6] makes us only report Supm when
userspace can choose non-zero PMLEN.

Based on v7.4-rc1 and even through there are a lot of Fixes: tags, there
isn't any rush to get this into 7.4, since the problems can only appear
in awkward/heterogenous platforms.


Radim Krčmář (6):
  riscv: hwprobe: Report FP extensions only when available
  riscv: hwprobe: Report Zicbom and Zicboz only when available
  riscv: hwprobe: Report Zicfilp and Zicfiss only when available
  riscv: hwprobe: Report Supm only when available
  riscv: hwprobe: Report XTheadVector only when available
  riscv: hwprobe: Report SiFive vector extensions only when available

 arch/riscv/include/asm/usercfi.h              |  9 ++--
 arch/riscv/kernel/sys_hwprobe.c               | 54 ++++++++++++-------
 .../kernel/vendor_extensions/sifive_hwprobe.c | 14 +++--
 .../kernel/vendor_extensions/thead_hwprobe.c  |  5 +-
 4 files changed, 54 insertions(+), 28 deletions(-)

-- 
2.55.0

[PATCH v2 1/6] riscv: hwprobe: Report FP extensions only when available

[Radim Krčmář]

User-mode use of floating-point extensions requires non-Off sstatus.FS,
which we set only when has_fpu() (CONFIG_FPU and D on all harts).
The vector floating-point extensions require non-Off sstatus.FS too, but
hwprobe gates them only on has_vector() (CONFIG_ISA_V and Zve32x on all
harts).

CONFIG_ISA_V depends on CONFIG_FPU, because V extension implies Zve64d,
but has_vector() only requires Zve32x, so has_vector() doesn't imply
has_fpu(), hence we can boot on a machine where all harts have Zve32x,
but not all harts have D.

hwprobe currently reports the extensions from the per-hart ISA bitmaps
alone, so it can advertise extensions that are always disabled in
user-mode.  Report correct environment to user-mode.

Fixes: 2e2cf5581fcc ("riscv: cpufeature: add validation for zfa, zfh and zfhmin")
Fixes: de8f8282a969 ("riscv: hwprobe: add zve Vector subextensions into hwprobe interface")
Fixes: 5dadda5e6a59 ("riscv: hwprobe: export Zvfh[min] ISA extensions")
Fixes: a4863e002cf0 ("riscv: hwprobe: export bfloat16 ISA extension")
Reviewed-by: Andy Chiu <tchiu@tenstorrent.com>
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
v2:
* added one more "Fixes:" for bfloat
* hopefully clarified the commit message around CONFIGs
* added r-b
---
 arch/riscv/kernel/sys_hwprobe.c | 31 ++++++++++++++++++-------------
 1 file changed, 18 insertions(+), 13 deletions(-)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index cd7cf272e6e1..feae40466e2b 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -146,15 +146,8 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		if (has_vector()) {
 			EXT_KEY(isainfo->isa, ZVBB, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVBC, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVE32X, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVE64X, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
-			EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKB, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKG, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKNED, pair->value, missing);
@@ -163,14 +156,26 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 			EXT_KEY(isainfo->isa, ZVKSED, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKSH, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZVKT, pair->value, missing);
+
+			if (has_fpu()) {
+				EXT_KEY(isainfo->isa, ZVE32F, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVE64D, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVE64F, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFBFMIN, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFBFWMA, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFH, pair->value, missing);
+				EXT_KEY(isainfo->isa, ZVFHMIN, pair->value, missing);
+			}
 		}
 
-		EXT_KEY(isainfo->isa, ZCD, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZCF, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFA, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFBFMIN, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
+		if (has_fpu()) {
+			EXT_KEY(isainfo->isa, ZCD, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZCF, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFA, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFBFMIN, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
+			EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
+		}
 
 		if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
 			EXT_KEY(isainfo->isa, SUPM, pair->value, missing);
-- 
2.55.0

[PATCH v2 2/6] riscv: hwprobe: Report Zicbom and Zicboz only when available

[Radim Krčmář]

User-mode use of Zicbom and Zicboz requires senvcfg.CBCFE and
senvcfg.CBZE, respectively, which we set only when all harts have the
extension.

hwprobe currently reports the extensions from the per-hart ISA bitmaps
alone, so it can advertise extensions that are always disabled in
user-mode.  Report correct environment to user-mode.

Fixes: 1b57747e978f ("riscv: Enable cbo.zero only when all harts support Zicboz")
Fixes: eb1003970940 ("RISC-V: hwprobe: Expose Zicbom extension and its block size")
Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
Reviewed-by: Andy Chiu <tchiu@tenstorrent.com>
Reviewed-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
v2:
* slightly reworded commit message
* added r-b
---
 arch/riscv/kernel/sys_hwprobe.c | 8 ++++++--
 1 file changed, 6 insertions(+), 2 deletions(-)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index feae40466e2b..73d5e25677a5 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -91,6 +91,12 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (has_vector() && riscv_isa_extension_available(NULL, V))
 		pair->value |= RISCV_HWPROBE_IMA_V;
 
+	if (riscv_isa_extension_available(NULL, ZICBOM))
+		pair->value |= RISCV_HWPROBE_EXT_ZICBOM;
+
+	if (riscv_isa_extension_available(NULL, ZICBOZ))
+		pair->value |= RISCV_HWPROBE_EXT_ZICBOZ;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -120,9 +126,7 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(isainfo->isa, ZCB, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZCLSD, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZCMOP, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZICBOM, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICBOP, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZICBOZ, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICFILP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICNTR, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICOND, pair->value, missing);
-- 
2.55.0

[PATCH v2 3/6] riscv: hwprobe: Report Zicfilp and Zicfiss only when available

[Radim Krčmář]

User-mode use of Zicfilp and Zicfiss requires senvcfg.LPE and
senvcfg.SSE, respectively, which we set only when is_user_lpad_enabled()
and is_user_shstk_enabled() (CONFIG_RISCV_USER_CFI, the extension on all
harts, and not disabled by riscv_nousercfi).

hwprobe currently reports the extensions from the per-hart ISA bitmaps
alone, so it can advertise extensions that are always disabled in
user-mode.  Report correct environment to user-mode.

The changes to arch/riscv/include/asm/usercfi.h avoid
IS_ENABLED(CONFIG_RISCV_USER_CFI) guards in the conditions.

Fixes: 30c3099036a9 ("riscv/hwprobe: add zicfilp / zicfiss enumeration in hwprobe")
Reviewed-by: Charlie Jenkins <thecharlesjenkins@gmail.com>
Reviewed-by: Andy Chiu <tchiu@tenstorrent.com>
Reviewed-by: Guodong Xu <guodong.xu@oss.qualcomm.com>
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
v2:
* slightly reworded commit message
* added r-b
---
 arch/riscv/include/asm/usercfi.h | 9 ++++++---
 arch/riscv/kernel/sys_hwprobe.c  | 9 +++++++--
 2 files changed, 13 insertions(+), 5 deletions(-)

diff --git a/arch/riscv/include/asm/usercfi.h b/arch/riscv/include/asm/usercfi.h
index 61ee02cee297..bbde171bccde 100644
--- a/arch/riscv/include/asm/usercfi.h
+++ b/arch/riscv/include/asm/usercfi.h
@@ -48,6 +48,8 @@ bool is_indir_lp_enabled(struct task_struct *task);
 bool is_indir_lp_locked(struct task_struct *task);
 void set_indir_lp_status(struct task_struct *task, bool enable);
 void set_indir_lp_lock(struct task_struct *task, bool lock);
+bool is_user_shstk_enabled(void);
+bool is_user_lpad_enabled(void);
 
 #define PR_SHADOW_STACK_SUPPORTED_STATUS_MASK (PR_SHADOW_STACK_ENABLE)
 #define PR_CFI_SUPPORTED_STATUS_MASK (PR_CFI_ENABLE | PR_CFI_DISABLE | PR_CFI_LOCK)
@@ -88,10 +90,11 @@ void set_indir_lp_lock(struct task_struct *task, bool lock);
 
 #define get_active_shstk(task) 0UL
 
-#endif /* CONFIG_RISCV_USER_CFI */
+static __always_inline bool is_user_shstk_enabled(void) { return false; }
 
-bool is_user_shstk_enabled(void);
-bool is_user_lpad_enabled(void);
+static __always_inline bool is_user_lpad_enabled(void) { return false; }
+
+#endif /* CONFIG_RISCV_USER_CFI */
 
 #endif /* __ASSEMBLER__ */
 
diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index 73d5e25677a5..a9aa1e193840 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -14,6 +14,7 @@
 #include <asm/switch_to.h>
 #include <asm/uaccess.h>
 #include <asm/unistd.h>
+#include <asm/usercfi.h>
 #include <asm/vector.h>
 #include <asm/vendor_extensions/mips_hwprobe.h>
 #include <asm/vendor_extensions/sifive_hwprobe.h>
@@ -97,6 +98,9 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (riscv_isa_extension_available(NULL, ZICBOZ))
 		pair->value |= RISCV_HWPROBE_EXT_ZICBOZ;
 
+	if (is_user_lpad_enabled())
+		pair->value |= RISCV_HWPROBE_EXT_ZICFILP;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -127,7 +131,6 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 		EXT_KEY(isainfo->isa, ZCLSD, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZCMOP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICBOP, pair->value, missing);
-		EXT_KEY(isainfo->isa, ZICFILP, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICNTR, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICOND, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZIHINTNTL, pair->value, missing);
@@ -197,6 +200,9 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 
 	pair->value = 0;
 
+	if (is_user_shstk_enabled())
+		pair->value |= RISCV_HWPROBE_EXT_ZICFISS;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -210,7 +216,6 @@ static void hwprobe_isa_ext1(struct riscv_hwprobe *pair,
 		 * configuration, as no other checks, besides presence
 		 * in the hart_isa bitmap, are made.
 		 */
-		EXT_KEY(isainfo->isa, ZICFISS, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCLSM, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCAMOA, pair->value, missing);
 		EXT_KEY(isainfo->isa, ZICCIF, pair->value, missing);
-- 
2.55.0

[PATCH v2 4/6] riscv: hwprobe: Report Supm only when available

[Radim Krčmář]

The RISC-V ISA defines Supm as

  "An extension that indicates that there is pointer-masking support
  available in user mode, with some facility provided in the application
  execution environment to control pointer masking."

Our facility, PR_{SET,GET}_TAGGED_ADDR_CTRL, always returns -EINVAL
unless CONFIG_RISCV_ISA_SUPM is enabled, Supm is present on all harts,
and the user-mode is running in 64-bit mode.

While we technically could advertise Supm even when it only supports
PMLEN=0, it seems a bit more useful to report Supm only in cases where
the userspace can configure non-zero pointer masking.
A minor downside of this approach is that we'll need to update the Supm
detection line when more pointer-masking modes get added.

hwprobe currently reports Supm from the per-hart ISA bitmaps alone, so
it can advertise Supm when the facility always returns -EINVAL.
Report slightly more precise environment to user-mode.

Hiding Supm in compat tasks would add complexity that doesn't seem
justified as 32-bit code has no reason to look at Supm anyway.
Reporting based on the global sysctl toggle isn't done either.

Fixes: 3c2e0aff7b4f ("riscv: hwprobe: Export the Supm ISA extension")
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
v2:
* Used pmlen helpers from v7.4-rc1 [Guodong]
* Updated commit message to reflect the reasoning
---
 arch/riscv/kernel/sys_hwprobe.c | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/riscv/kernel/sys_hwprobe.c b/arch/riscv/kernel/sys_hwprobe.c
index a9aa1e193840..21738e2539a8 100644
--- a/arch/riscv/kernel/sys_hwprobe.c
+++ b/arch/riscv/kernel/sys_hwprobe.c
@@ -101,6 +101,9 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 	if (is_user_lpad_enabled())
 		pair->value |= RISCV_HWPROBE_EXT_ZICFILP;
 
+	if (riscv_have_user_pmlen(7) || riscv_have_user_pmlen(16))
+		pair->value |= RISCV_HWPROBE_EXT_SUPM;
+
 	/*
 	 * Loop through and record extensions that 1) anyone has, and 2) anyone
 	 * doesn't have.
@@ -183,9 +186,6 @@ static void hwprobe_isa_ext0(struct riscv_hwprobe *pair,
 			EXT_KEY(isainfo->isa, ZFH, pair->value, missing);
 			EXT_KEY(isainfo->isa, ZFHMIN, pair->value, missing);
 		}
-
-		if (IS_ENABLED(CONFIG_RISCV_ISA_SUPM))
-			EXT_KEY(isainfo->isa, SUPM, pair->value, missing);
 	}
 
 	/* Now turn off reporting features if any CPU is missing it. */
-- 
2.55.0

[PATCH v2 5/6] riscv: hwprobe: Report XTheadVector only when available

[Radim Krčmář]

User-mode use of XTheadVector requires non-Off sstatus.VS, which we set
only when has_xtheadvector() (XTheadVector on all harts).
XTheadVector also bundles operations with floating state, which
additionally requires non-Off sstatus.FS and hence has_fpu() (D on all
harts).

hwprobe currently reports XTheadVector from the per-hart ISA bitmaps
alone, so it can advertise XTheadVector when always disabled in
user-mode.  Report correct environment to user-mode.

Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing")
Reviewed-by: Andy Chiu <tchiu@tenstorrent.com>
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
v2:
* slightly reworded commit message
* added r-b
---
 arch/riscv/kernel/vendor_extensions/thead_hwprobe.c | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
index 2eba34011786..f07aa1c8acac 100644
--- a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
+++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
+#include <asm/switch_to.h>
+#include <asm/vector.h>
 #include <asm/vendor_extensions/thead.h>
 #include <asm/vendor_extensions/thead_hwprobe.h>
 #include <asm/vendor_extensions/vendor_hwprobe.h>
@@ -14,6 +16,7 @@ void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpu
 {
 	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
 				   riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, {
-		VENDOR_EXT_KEY(XTHEADVECTOR);
+		if (has_xtheadvector() && has_fpu())
+			VENDOR_EXT_KEY(XTHEADVECTOR);
 	});
 }
-- 
2.55.0

[PATCH v2 6/6] riscv: hwprobe: Report SiFive vector extensions only when available

[Radim Krčmář]

User-mode use of the SiFive vector extensions requires non-Off
sstatus.VS, which we set only when has_vector() (Zve32x on all harts).
Xsfvfnrclipxfqf and Xsfvfwmaccqqq also execute floating-point
instructions, which additionally require non-Off sstatus.FS and hence
has_fpu() (D on all harts).

hwprobe currently reports the extensions from the per-hart ISA bitmaps
alone, so it can advertise extensions that are always disabled in
user-mode.  Report correct environment to user-mode.

Fixes: 1a6274f03534 ("riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq")
Fixes: 1d91224394c9 ("riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension")
Fixes: d9669e33c8fa ("riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension")
Reviewed-by: Andy Chiu <tchiu@tenstorrent.com>
Signed-off-by: Radim Krčmář <radim.krcmar@oss.qualcomm.com>
---
v2:
* slightly reworded commit message
* added r-b
---
 .../kernel/vendor_extensions/sifive_hwprobe.c      | 14 ++++++++++----
 1 file changed, 10 insertions(+), 4 deletions(-)

diff --git a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
index 1f77f6309763..bcea4f7a81c4 100644
--- a/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
+++ b/arch/riscv/kernel/vendor_extensions/sifive_hwprobe.c
@@ -1,5 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0-only
 
+#include <asm/switch_to.h>
+#include <asm/vector.h>
 #include <asm/vendor_extensions/sifive.h>
 #include <asm/vendor_extensions/sifive_hwprobe.h>
 #include <asm/vendor_extensions/vendor_hwprobe.h>
@@ -14,9 +16,13 @@ void hwprobe_isa_vendor_ext_sifive_0(struct riscv_hwprobe *pair, const struct cp
 {
 	VENDOR_EXTENSION_SUPPORTED(pair, cpus,
 				   riscv_isa_vendor_ext_list_sifive.per_hart_isa_bitmap, {
-		VENDOR_EXT_KEY(XSFVQMACCDOD);
-		VENDOR_EXT_KEY(XSFVQMACCQOQ);
-		VENDOR_EXT_KEY(XSFVFNRCLIPXFQF);
-		VENDOR_EXT_KEY(XSFVFWMACCQQQ);
+		if (has_vector()) {
+			VENDOR_EXT_KEY(XSFVQMACCDOD);
+			VENDOR_EXT_KEY(XSFVQMACCQOQ);
+			if (has_fpu()) {
+				VENDOR_EXT_KEY(XSFVFNRCLIPXFQF);
+				VENDOR_EXT_KEY(XSFVFWMACCQQQ);
+			}
+		}
 	});
 }
-- 
2.55.0