[PATCH net-next v2 0/2] net: stmmac: dwmac-socfpga: Add Agilex5 TSN GMAC support

[PATCH net-next v2 0/2] net: stmmac: dwmac-socfpga: Add Agilex5 TSN GMAC support

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

This series adds support for the gmac1 TSN port on the Intel SoCFPGA
Agilex5 SoCDK TSN Config2 board.

The TSN port (gmac1) connects to its PHY through a GMII-to-RGMII converter
implemented as FPGA soft IP. This converter provides the RGMII TX/RX clock
delays, requiring the MAC interface selector to be configured for GMII while
the PHY-facing interface is configured as RGMII without delay duplication.

Patch 1 documents the altr,socfpga-stmmac-agilex5-tsn compatible. Patch 2
adds dedicated match .data ops for the required interface setup.

The board-level binding and DTS patches will be sent separately to the
SoCFPGA tree.

This is a reposted version with a fix based on Jakub Kicinski's review:
https://lore.kernel.org/all/20260928184340.51da489c@kernel.org/

v2:
  - Extend the interrupt/interrupt-names/dma-coherent allOf conditional in
    the net binding to match altr,socfpga-stmmac-agilex5-tsn, per Jakub
    Kicinski / the netdev review bot. The TSN port uses the same
    DWXGMAC-2.10 core, so it must take the 17-interrupt, dma-coherent
    branch rather than the single-interrupt else branch.

These two patches were previously posted as patches 3 and 4 of the
"Add Agilex5 SoCDK TSN Config2 board support" series (up to v6), then
reposted as a standalone net-next series per Jakub Kicinski's request.
History from the board series:

v6:
  - Put altr,socfpga-stmmac-agilex5-tsn in the same compatible enum as
    altr,socfpga-stmmac-agilex5 in the net binding, per Krzysztof Kozlowski.

v5:
  - Replace of_device_is_compatible() probe check with dedicated
    socfpga_agilex5_tsn_gmac_ops via match .data, per Krzysztof Kozlowski
    and Dinh Nguyen.
  - Drop altr,socfpga-stmmac-agilex5 fallback from the TSN compatible list
    and rewrite the net binding commit message to explain the hardware
    difference, per Krzysztof Kozlowski.

v4:
  - Add Reviewed-by from Andrew Lunn on the driver patch.

v2 (board series):
  - Replace mac-mode DT property with compatible string-based detection per
    Andrew Lunn's feedback.
  - Use phy-mode = "rgmii-id" to correctly reflect MAC-side delay handling.
  - Rename compatible string to altr,socfpga-stmmac-agilex5-tsn for
    consistency with existing altr,socfpga-stmmac-* compatibles.
  - Add DT binding documentation for new net compatible string (new patch).

Nazim Amirul (2):
  dt-bindings: net: altr,socfpga-stmmac: Add
    altr,socfpga-stmmac-agilex5-tsn compatible
  net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA
    converter

 .../bindings/net/altr,socfpga-stmmac.yaml     |  9 ++++++--
 .../ethernet/stmicro/stmmac/dwmac-socfpga.c   | 23 ++++++++++++++++++-
 2 files changed, 29 insertions(+), 3 deletions(-)

-- 
2.43.7

[PATCH net-next v2 1/2] dt-bindings: net: altr,socfpga-stmmac: Add altr,socfpga-stmmac-agilex5-tsn compatible

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The Agilex5 SoCDK TSN Config2 gmac1 path includes an FPGA soft-IP
GMII-to-RGMII converter between the DWXGMAC and the PHY. The converter
provides the RGMII TX/RX delays and presents GMII toward the MAC, unlike
a plain altr,socfpga-stmmac-agilex5 port with no such converter.

Add altr,socfpga-stmmac-agilex5-tsn for that integration in the same
compatible items entry as altr,socfpga-stmmac-agilex5 (shared
snps,dwxgmac-2.10). Do not use altr,socfpga-stmmac-agilex5 as a DT
fallback for the TSN port; the converter presents GMII to the MAC and
supplies the RGMII delays, unlike a plain Agilex5 GMAC port.

The TSN port uses the same DWXGMAC-2.10 core as the plain Agilex5 port,
so extend the interrupt/interrupt-names/dma-coherent conditional to
match the new compatible as well; otherwise a TSN node would incorrectly
fall into the single-interrupt, non-coherent else branch.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
---
Previously patch 3 of the v6 board series; split out for net-next.

v2: Extend the interrupt/interrupt-names/dma-coherent allOf conditional to
    match altr,socfpga-stmmac-agilex5-tsn, per Jakub Kicinski / netdev bot.
v6: Put altr,socfpga-stmmac-agilex5-tsn in the same enum as
    altr,socfpga-stmmac-agilex5, per Krzysztof Kozlowski.
v5: Drop altr,socfpga-stmmac-agilex5 fallback and rewrite commit message
    to explain hardware incompatibility, per Krzysztof Kozlowski.

 .../devicetree/bindings/net/altr,socfpga-stmmac.yaml     | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
index ce1bd5f2c470..a6ffd7b98c1d 100644
--- a/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
+++ b/Documentation/devicetree/bindings/net/altr,socfpga-stmmac.yaml
@@ -22,6 +22,7 @@ select:
           - altr,socfpga-stmmac
           - altr,socfpga-stmmac-a10-s10
           - altr,socfpga-stmmac-agilex5
+          - altr,socfpga-stmmac-agilex5-tsn
 
   required:
     - compatible
@@ -42,7 +43,9 @@ properties:
           - const: snps,dwmac-3.74a
           - const: snps,dwmac
       - items:
-          - const: altr,socfpga-stmmac-agilex5
+          - enum:
+              - altr,socfpga-stmmac-agilex5
+              - altr,socfpga-stmmac-agilex5-tsn
           - const: snps,dwxgmac-2.10
 
   clocks:
@@ -178,7 +181,9 @@ allOf:
       properties:
         compatible:
           contains:
-            const: altr,socfpga-stmmac-agilex5
+            enum:
+              - altr,socfpga-stmmac-agilex5
+              - altr,socfpga-stmmac-agilex5-tsn
     then:
       properties:
         interrupts:
-- 
2.43.7

[PATCH net-next v2 2/2] net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter

[muhammad.nazim.amirul.nazle.asmade]

From: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>

The Agilex5 SoCDK TSN Config2 board uses a GMII-to-RGMII converter
implemented as FPGA soft IP between gmac1 and its PHY. This converter
provides the RGMII TX/RX clock delays, so the MAC interface selector
must be configured for GMII while the PHY is configured without delays.

Add the "altr,socfpga-stmmac-agilex5-tsn" compatible with dedicated
match .data ops that extend the standard Agilex5 setup: force GMII for
the MAC interface selector and strip delay bits from phy_interface so
the PHY is not configured to add delays already provided by the FPGA
converter.

Signed-off-by: Nazim Amirul <muhammad.nazim.amirul.nazle.asmade@altera.com>
Reviewed-by: Andrew Lunn <andrew@lunn.ch>
Reviewed-by: Maxime Chevallier <maxime.chevallier@bootlin.com>
---
Previously patch 4 of the v6 board series; split out for net-next.

v2: No driver changes. The netdev bot's note about rewriting every RGMII
    variant to plain rgmii is intentional (the FPGA converter supplies the
    delays); confirmed a non-issue given Andrew Lunn's Reviewed-by.
v6: No changes from v5.
v5: Replace of_device_is_compatible() probe check with dedicated
    socfpga_agilex5_tsn_gmac_ops via match .data, per Krzysztof
    Kozlowski and Dinh Nguyen.
v4: Add Reviewed-by from Andrew Lunn.

 .../ethernet/stmicro/stmmac/dwmac-socfpga.c   | 23 ++++++++++++++++++-
 1 file changed, 22 insertions(+), 1 deletion(-)

diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
index 6d4bc1fe8f75..131d2a98c863 100644
--- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
+++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
@@ -69,12 +69,13 @@ struct socfpga_dwmac {
 	void __iomem *tse_pcs_base;
 	void __iomem *sgmii_adapter_base;
 	bool f2h_ptp_ref_clk;
+	phy_interface_t mac_interface;
 	const struct socfpga_dwmac_ops *ops;
 };
 
 static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
 {
-	return dwmac->plat_dat->phy_interface;
+	return dwmac->mac_interface;
 }
 
 static void socfpga_sgmii_config(struct socfpga_dwmac *dwmac, bool enable)
@@ -653,6 +654,8 @@ static int socfpga_dwmac_probe(struct platform_device *pdev)
 	plat_dat->pcs_exit = socfpga_dwmac_pcs_exit;
 	plat_dat->select_pcs = socfpga_dwmac_select_pcs;
 
+	dwmac->mac_interface = plat_dat->phy_interface;
+
 	ops->setup_plat_dat(dwmac);
 
 	return devm_stmmac_pltfr_probe(pdev, plat_dat, &stmmac_res);
@@ -673,10 +676,28 @@ static const struct socfpga_dwmac_ops socfpga_agilex5_ops = {
 	.setup_plat_dat = socfpga_agilex5_setup_plat_dat,
 };
 
+static void socfpga_agilex5_tsn_gmac_setup_plat_dat(struct socfpga_dwmac *dwmac)
+{
+	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
+
+	socfpga_agilex5_setup_plat_dat(dwmac);
+
+	/* FPGA converter supplies RGMII delays; MAC uses GMII, PHY gets plain RGMII */
+	dwmac->mac_interface = PHY_INTERFACE_MODE_GMII;
+	if (phy_interface_mode_is_rgmii(plat_dat->phy_interface))
+		plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII;
+}
+
+static const struct socfpga_dwmac_ops socfpga_agilex5_tsn_gmac_ops = {
+	.set_phy_mode = socfpga_gen10_set_phy_mode,
+	.setup_plat_dat = socfpga_agilex5_tsn_gmac_setup_plat_dat,
+};
+
 static const struct of_device_id socfpga_dwmac_match[] = {
 	{ .compatible = "altr,socfpga-stmmac", .data = &socfpga_gen5_ops },
 	{ .compatible = "altr,socfpga-stmmac-a10-s10", .data = &socfpga_gen10_ops },
 	{ .compatible = "altr,socfpga-stmmac-agilex5", .data = &socfpga_agilex5_ops },
+	{ .compatible = "altr,socfpga-stmmac-agilex5-tsn", .data = &socfpga_agilex5_tsn_gmac_ops },
 	{ }
 };
 MODULE_DEVICE_TABLE(of, socfpga_dwmac_match);
-- 
2.43.7

Re: [PATCH net-next v2 2/2] net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter

[Jakub Kicinski]

This is an AI-generated review of your patch. The human sending this
email has considered the AI review valid, or at least plausible.
---
net: stmmac: dwmac-socfpga: Add support for Agilex5 TSN GMAC with FPGA converter

This adds the "altr,socfpga-stmmac-agilex5-tsn" compatible for Agilex5
boards where an FPGA GMII-to-RGMII converter between the MAC and the PHY
supplies the RGMII delays. socfpga_get_plat_phymode() now returns a new
mac_interface field. The new setup_plat_dat callback forces that field
to GMII and rewrites any RGMII phy_interface to plain RGMII.

> diff --git a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> index 6d4bc1fe8f751..131d2a98c863f 100644
> --- a/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c
> +++ b/drivers/net/ethernet/stmicro/stmmac/dwmac-socfpga.c

[ ... ]

>  static phy_interface_t socfpga_get_plat_phymode(struct socfpga_dwmac *dwmac)
>  {
> -	return dwmac->plat_dat->phy_interface;
> +	return dwmac->mac_interface;
>  }

[Severity: Low]
This isn't a bug, but socfpga_gen5_set_phy_mode() and
socfpga_gen10_set_phy_mode() both still have this comment:

	/* Overwrite val to GMII if splitter core is enabled. The phymode here
	 * is the actual phy mode on phy hardware, but phy interface from
	 * EMAC core is GMII.
	 */

After this change, phymode comes from dwmac->mac_interface, which is the
MAC-side mode. For the agilex5-tsn compatible it is GMII while the PHY
runs RGMII, so the comment now says the opposite of what phymode holds.

Should the comment be updated to match the new meaning? The same applies
to the name socfpga_get_plat_phymode().

[ ... ]

> @@ -673,10 +676,28 @@ static const struct socfpga_dwmac_ops socfpga_agilex5_ops = {
>  	.setup_plat_dat = socfpga_agilex5_setup_plat_dat,
>  };
>  
> +static void socfpga_agilex5_tsn_gmac_setup_plat_dat(struct socfpga_dwmac *dwmac)
> +{
> +	struct plat_stmmacenet_data *plat_dat = dwmac->plat_dat;
> +
> +	socfpga_agilex5_setup_plat_dat(dwmac);
> +
> +	/* FPGA converter supplies RGMII delays; MAC uses GMII, PHY gets plain RGMII */
> +	dwmac->mac_interface = PHY_INTERFACE_MODE_GMII;

[Severity: Medium]
mac_interface is forced to GMII for every phy-mode. phy_interface is only
rewritten for RGMII variants. What happens with phy-mode "sgmii" or
"1000base-x"? The altr,socfpga-stmmac.yaml phy-mode enum allows both for
this compatible.

In that case socfpga_get_plat_phymode() returns GMII.
socfpga_dwmac_fix_mac_speed() then disables the SGMII adapter on every
link-up and never turns it back on:

	if (sgmii_adapter_base)
		socfpga_sgmii_config(dwmac, false);
	...
	if ((phymode == PHY_INTERFACE_MODE_SGMII ||
	     phymode == PHY_INTERFACE_MODE_1000BASEX) && sgmii_adapter_base)
		socfpga_sgmii_config(dwmac, true);

socfpga_gen10_set_phy_mode() also skips its final enable:

	if (phymode == PHY_INTERFACE_MODE_SGMII)
		socfpga_sgmii_config(dwmac, true);

Meanwhile phylink and the Lynx PCS keep using the DT mode. The
GMII-to-SGMII adapter would stay disabled while an SGMII or 1000base-x
link comes up, and nothing reports the problem.

Should the GMII override also be guarded by phy_interface_mode_is_rgmii()?
The other option would be to reject non-RGMII modes for this compatible.

> +	if (phy_interface_mode_is_rgmii(plat_dat->phy_interface))
> +		plat_dat->phy_interface = PHY_INTERFACE_MODE_RGMII;

[Severity: Medium]
If the converter always adds both the TX and RX delays, rgmii-id seems to
be the only phy-mode that describes the board consistently. Is that
right?

"rgmii", "rgmii-txid" and "rgmii-rxid" each describe the PCB as providing
the delay in at least one direction. The converter would then add its
delay on top of that. This code rewrites all of them to plain RGMII
without a warning, so the link could fail with no diagnostic.

The stmmac core already handles MACs with fixed internal delays. With
plat_dat->has_internal_tx_delay and has_internal_rx_delay set (as
dwmac-ultrarisc.c does), stmmac_pltfr_probe() runs:

	if (plat->has_internal_tx_delay || plat->has_internal_rx_delay) {
		plat->phy_interface =
			phy_fix_phy_mode_for_mac_delays(plat->phy_interface,
							plat->has_internal_tx_delay,
							plat->has_internal_rx_delay);
		if (plat->phy_interface == PHY_INTERFACE_MODE_NA)
			return dev_err_probe(&pdev->dev, -EINVAL,
					     "unsupported phy interface mode\n");
	}

When both delays are set, phy_fix_phy_mode_for_mac_delays() maps rgmii-id
to rgmii and returns PHY_INTERFACE_MODE_NA for the other three modes:

	if (mac_txid && mac_rxid) {
		if (interface == PHY_INTERFACE_MODE_RGMII_ID)
			return PHY_INTERFACE_MODE_RGMII;
		return PHY_INTERFACE_MODE_NA;
	}

Documentation/devicetree/bindings/net/ethernet-controller.yaml says this
about MACs with hard coded delays:

  It does however mean that a 'phy-mode' of 'rgmii' is now invalid, it
  cannot be supported, [...] Thus the MAC should report a fatal error for
  any modes which cannot be supported.

Could has_internal_tx_delay and has_internal_rx_delay replace the
open-coded rewrite here? Then inconsistent phy-modes would be rejected at
probe time.

> +}
> +
> +static const struct socfpga_dwmac_ops socfpga_agilex5_tsn_gmac_ops = {
> +	.set_phy_mode = socfpga_gen10_set_phy_mode,
> +	.setup_plat_dat = socfpga_agilex5_tsn_gmac_setup_plat_dat,
> +};

[ ... ]