From: Agustin Santiago Isasmendi <isasmendi.agus@gmail.com>
To: Russell King <linux@armlinux.org.uk>
Cc: linux-arm-kernel@lists.infradead.org,
linux-kernel@vger.kernel.org, "Arnd Bergmann" <arnd@arndb.de>,
"Stefan Dösinger" <stefandoesinger@gmail.com>,
"Navid Ghahremani" <ghahramani.navid@gmail.com>,
"Krzysztof Kozlowski" <krzk@kernel.org>
Subject: [PATCH 0/2] ARM: l2c: honour status = "disabled" on the L2 cache node
Date: Wed, 11 Nov 2026 14:39:28 +0100 [thread overview]
Message-ID: <20261111133930.3665251-1-isasmendi.agus@gmail.com> (raw)
Hi Russell,
l2x0_of_init() finds the L2 cache node by compatible and never looks at
its status property, so a device tree cannot keep the L2 cache off.
Patch 2 makes it honour status = "disabled", as the newer cache
controller drivers in drivers/cache/ already do. If the firmware left
the cache enabled it cannot just be ignored, since nothing would
maintain it, so it is cleaned, invalidated and disabled instead. Patch 1 moves
the number-of-ways computation out of the per-part init code so that
the disable path can reuse it.
The user is the ZTE ZX279128S (dual Cortex-A9, L2C-310 r3p3), where a
PCIe read on one CPU deadlocks against an L2C-310 line operation by
physical address or a Cache Sync on the other CPU, and the board hangs
within seconds of WiFi traffic. Running with the L2 cache off avoids
it, and that was suggested as the fallback for the platform when a
lock-based workaround was found too invasive for generic code:
https://lore.kernel.org/r/20261110153522.1620088-1-isasmendi.agus@gmail.com
Whether the ZX279128S device tree disables the cache is a decision for
that thread; this series only makes the property work.
No in-tree L2 cache node is disabled, so existing device trees are not
affected. Tested on the ZTE ZXHN H3600 (not in mainline yet, on top of
Navid Ghahremani's v2 platform series): with the node disabled the cache
stays off (control register 0) and the system runs normally; with it
enabled the cache comes up as before; the firmware-enabled path was
exercised with a test-only change that enables the cache before the
check. Builds without warnings with W=1 (board config and
multi_v7_defconfig); checkpatch --strict is clean.
Agustin Santiago Isasmendi (2):
ARM: l2c: factor out the number of ways
ARM: l2c: honour status = "disabled" on the L2 cache node
arch/arm/mm/cache-l2x0.c | 85 ++++++++++++++++++++++++++++------------
1 file changed, 59 insertions(+), 26 deletions(-)
base-commit: c03c1a14507dfaf8b856c2608f9ac216021fc222
--
2.30.2
next reply other threads:[~2026-11-11 13:39 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-11 13:39 Agustin Santiago Isasmendi [this message]
2026-11-11 13:39 ` [PATCH 1/2] ARM: l2c: factor out the number of ways Agustin Santiago Isasmendi
2026-11-11 14:24 ` Arnd Bergmann
2026-11-11 13:39 ` [PATCH 2/2] ARM: l2c: honour status = "disabled" on the L2 cache node Agustin Santiago Isasmendi
2026-11-11 13:56 ` Arnd Bergmann
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