[PATCH] drm/msm/adreno: Improve AHB error messages

[PATCH] drm/msm/adreno: Improve AHB error messages

[Rob Clark]

On a7xx/a8xx we can get some details out of the CP_RL_ERROR_DETAILS
registers.

Signed-off-by: Rob Clark <robin.clark@oss.qualcomm.com>
---
 drivers/gpu/drm/msm/adreno/a6xx_gpu.c         | 20 +++++++++++++++++--
 drivers/gpu/drm/msm/adreno/a8xx_gpu.c         | 10 ++++++++--
 drivers/gpu/drm/msm/registers/adreno/a6xx.xml | 11 +++++++++-
 3 files changed, 36 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
index a93e9c960d88..484a78dbc804 100644
--- a/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a6xx_gpu.c
@@ -1957,8 +1957,24 @@ static irqreturn_t a6xx_irq(struct msm_gpu *gpu)
 	if (status & A6XX_RBBM_INT_0_MASK_RBBM_HANG_DETECT)
 		a6xx_fault_detect_irq(gpu);
 
-	if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR)
-		dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
+	if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
+		if (adreno_is_a7xx(to_adreno_gpu(gpu))) {
+			u32 rl0, rl1, addr;
+			const char *mode;
+
+			rl0 = gpu_read(gpu, REG_A7XX_CP_RL_ERROR_DETAILS_0);
+			rl1 = gpu_read(gpu, REG_A7XX_CP_RL_ERROR_DETAILS_1);
+
+			addr = FIELD(rl0, A7XX_CP_RL_ERROR_DETAILS_0_ADDR);
+			mode = (rl0 & A7XX_CP_RL_ERROR_DETAILS_0_WRITE) ? "write" : "read";
+
+			dev_err_ratelimited(&gpu->pdev->dev,
+				"CP | AHB bus error RL_ERROR_0: %x (addr: 0x%05x, %s), RL_ERROR_1: %x\n",
+				rl0, addr, mode, rl1);
+		} else {
+			dev_err_ratelimited(&gpu->pdev->dev, "CP | AHB bus error\n");
+		}
+	}
 
 	if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
 		a6xx_cp_hw_err_irq(gpu);
diff --git a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
index f6afa5b3b0bb..bbf5ca4fb6fc 100644
--- a/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
+++ b/drivers/gpu/drm/msm/adreno/a8xx_gpu.c
@@ -1248,12 +1248,18 @@ irqreturn_t a8xx_irq(struct msm_gpu *gpu)
 		a8xx_fault_detect_irq(gpu);
 
 	if (status & A6XX_RBBM_INT_0_MASK_CP_AHB_ERROR) {
-		u32 rl0, rl1;
+		u32 rl0, rl1, addr;
+		const char *mode;
 
 		rl0 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_0);
 		rl1 = gpu_read(gpu, REG_A8XX_CP_RL_ERROR_DETAILS_1);
+
+		addr = FIELD(rl0, A8XX_CP_RL_ERROR_DETAILS_0_ADDR);
+		mode = (rl0 & A8XX_CP_RL_ERROR_DETAILS_0_WRITE) ? "write" : "read";
+
 		dev_err_ratelimited(&gpu->pdev->dev,
-				"CP | AHB bus error RL_ERROR_0: %x, RL_ERROR_1: %x\n", rl0, rl1);
+			"CP | AHB bus error RL_ERROR_0: %x (addr: 0x%05x, %s), RL_ERROR_1: %x\n",
+			rl0, addr, mode, rl1);
 	}
 
 	if (status & A6XX_RBBM_INT_0_MASK_CP_HW_ERROR)
diff --git a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
index b1e7dd26e98a..8d33d9285007 100644
--- a/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
+++ b/drivers/gpu/drm/msm/registers/adreno/a6xx.xml
@@ -193,7 +193,16 @@ by a particular renderpass/blit.
 		<reg32 offset="0x0" name="REG"/>
 	</array>
 
-	<reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-"/>
+	<reg32 offset="0x09b4" name="CP_RL_ERROR_DETAILS_0" variants="A7XX">
+		<bitfield name="ADDR" low="0" high="19"/>
+		<bitfield name="WRITE" pos="28" type="boolean"/>
+	</reg32>
+	<reg32 offset="0x09cf" name="CP_RL_ERROR_DETAILS_1" variants="A7XX"/>
+
+	<reg32 offset="0x0840" name="CP_RL_ERROR_DETAILS_0" variants="A8XX-">
+		<bitfield name="ADDR" low="0" high="19"/>
+		<bitfield name="WRITE" pos="28" type="boolean"/>
+	</reg32>
 	<reg32 offset="0x0841" name="CP_RL_ERROR_DETAILS_1" variants="A8XX-"/>
 
 	<reg64 offset="0x0830" name="CP_SQE_INSTR_BASE" variants="A6XX-A7XX"/>
-- 
2.56.0