[PATCH net v2] octeontx2-af: fix TX scheduler queue index width for CN20K

[kmahammadraf <kmahammadraf@marvell.com>]

From: Satha Rao <skoteshwar@marvell.com>

CN20K supports up to 2K TX scheduler queues per layer, so scheduler queue
index handling must use 11 bits.

Update TX scheduler queue index handling in both register-address decoding
and hierarchy parent validation paths. Also widen TX scheduler register
masking used by mailbox/config register access.

Without this, queue IDs above 1023 can be truncated on CN20K, which can
cause invalid hierarchy validation and incorrect TX scheduler register
access for higher queue indices.

Fixes: b279bbb3314e ("octeontx2-af: NIX Tx scheduler queue config support")
Fixes: d06411632e80 ("octeontx2-af: enable tx shaping feature for 96xx C0")

Signed-off-by: kmahammadraf <kmahammadraf@marvell.com>
Signed-off-by: Satha Rao <skoteshwar@marvell.com>
---
v2: https://lore.kernel.org/netdev/179264357442.3290.13030103983603784553@kernel.org/
	- Fix parent scheduler index decoding in hierarchy validation for CN20K.
	- Add Fixes tags for the affected TX scheduler index/mask paths.
	- Correct commit subject formatting (remove nested "Subject: [PATCH]" text).
---
 drivers/net/ethernet/marvell/octeontx2/af/mbox.h    | 2 +-
 drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c | 6 +++---
 2 files changed, 4 insertions(+), 4 deletions(-)

diff --git a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
index cece197d1074..1b62f9d7f00a 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
+++ b/drivers/net/ethernet/marvell/octeontx2/af/mbox.h
@@ -1164,7 +1164,7 @@ struct nix_txschq_config {
 	u8 lvl;	/* SMQ/MDQ/TL4/TL3/TL2/TL1 */
 	u8 read;
 #define TXSCHQ_IDX_SHIFT	16
-#define TXSCHQ_IDX_MASK		(BIT_ULL(10) - 1)
+#define TXSCHQ_IDX_MASK		(BIT_ULL(11) - 1)
 #define TXSCHQ_IDX(reg, shift)	(((reg) >> (shift)) & TXSCHQ_IDX_MASK)
 	u8 num_regs;
 #define MAX_REGS_PER_MBOX_MSG	20
diff --git a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
index 29559db68929..72d13d34829d 100644
--- a/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
+++ b/drivers/net/ethernet/marvell/octeontx2/af/rvu_nix.c
@@ -2755,7 +2755,7 @@ static bool is_txschq_hierarchy_valid(struct rvu *rvu, u16 pcifunc, int blkaddr,
 	if (!is_valid_txschq(rvu, blkaddr, lvl, pcifunc, schq))
 		return false;
 
-	parent = (regval >> 16) & 0x1FF;
+	parent = (regval >> 16) & (is_cn20k(rvu->pdev) ? 0x7FF : 0x1FF);
 	/* Validate MDQ's TL4 parent */
 	if (regbase == NIX_AF_MDQX_PARENT(0) &&
 	    !is_valid_txschq(rvu, blkaddr, NIX_TXSCH_LVL_TL4, pcifunc, parent))
@@ -2849,9 +2849,9 @@ static void nix_tl1_default_cfg(struct rvu *rvu, struct nix_hw *nix_hw,
 }
 
 /* Register offset - [15:0]
- * Scheduler Queue number - [25:16]
+ * Scheduler Queue number - [26:16]
  */
-#define NIX_TX_SCHQ_MASK	GENMASK_ULL(25, 0)
+#define NIX_TX_SCHQ_MASK	GENMASK_ULL(26, 0)
 
 static int nix_txschq_cfg_read(struct rvu *rvu, struct nix_hw *nix_hw,
 			       int blkaddr, struct nix_txschq_config *req,
-- 
2.25.1