[PATCH v4 11/21] KVM: x86/pmu: Document GLOBAL_STATUS_RESET passthrough erratum

[Zide Chen <zide.chen@intel.com>]

IA32_PERF_GLOBAL_STATUS_RESET, introduced in PerfMon version 4,
inherits the MSR address and architecturally defined bits from
IA32_PERF_GLOBAL_OVF_CTRL, while providing additional bits to clear
new indicators in IA32_PERF_GLOBAL_STATUS.

From an emulation perspective, KVM handles it identically to the legacy
OVF_CTRL MSR: reads return zero, and intercepted writes are guarded
against pmu->global_status_rsvd. No code changes are needed in KVM
to emulate this MSR.

However, to reduce VM-exits on performance-critical paths, KVM passes
through this MSR in mediated PMU mode when all hardware counters are
exposed to the guest. Consequently, writes to bits that are valid in
hardware but unvirtualized by KVM will not trigger #GP (unlike when
intercepted). This is safe because such unvirtualized bits are never set
while the guest runs, so clearing them has no effect, and because the
MSR is read-as-zero and write-to-clear, passing it through cannot leak
host state.

Document this divergence in errata.rst.

Signed-off-by: Zide Chen <zide.chen@intel.com>
Reviewed-by: Jim Mattson <jmattson@google.com>
---
v4:
- Clarify in errata.rst that passthrough occurs when all hardware
  counters are exposed to the guest, and that guest writes cannot
  clobber host state. (Yosry)

v3:
- New patch. (Jim)
---
 Documentation/virt/kvm/x86/errata.rst | 10 +++++++++-
 1 file changed, 9 insertions(+), 1 deletion(-)

diff --git a/Documentation/virt/kvm/x86/errata.rst b/Documentation/virt/kvm/x86/errata.rst
index a9cf0e004651..70fd8a638ef7 100644
--- a/Documentation/virt/kvm/x86/errata.rst
+++ b/Documentation/virt/kvm/x86/errata.rst
@@ -84,4 +84,12 @@ memory.
 
 Note, this erratum does not affect AMD CPUs, which fully virtualize CR0.CD in
 hardware, i.e. put the CPU caches into "no fill" mode when CR0.CD=1, even when
-running in the guest.
\ No newline at end of file
+running in the guest.
+
+IA32_PERF_GLOBAL_STATUS_RESET
+-----------------------------
+To reduce VM-exits on performance-critical paths, KVM passes through writes
+to IA32_PERF_GLOBAL_STATUS_RESET (0x390) in mediated PMU mode when all
+hardware counters are exposed to the guest, without injecting #GP on
+unvirtualized bits.  Because the MSR is read-as-zero and write-to-clear, this
+cannot leak host information or clobber host state.
-- 
2.56.1