From: Zide Chen <zide.chen@intel.com>
To: Sean Christopherson <seanjc@google.com>,
Paolo Bonzini <pbonzini@redhat.com>,
Peter Zijlstra <peterz@infradead.org>
Cc: kvm@vger.kernel.org, Jim Mattson <jmattson@google.com>,
Yosry Ahmed <yosry@kernel.org>, Andi Kleen <ak@linux.intel.com>,
Stephane Eranian <eranian@google.com>,
linux-kernel@vger.kernel.org, Mingwei Zhang <mizhang@google.com>,
Zide Chen <zide.chen@intel.com>,
Das Sandipan <Sandipan.Das@amd.com>,
Shukla Manali <Manali.Shukla@amd.com>,
Dapeng Mi <dapeng1.mi@linux.intel.com>,
Xudong Hao <xudong.hao@intel.com>
Subject: [PATCH v4 16/21] KVM: x86/pmu: Populate CPUID.0AH:ECX fixed-counter bitmap
Date: Thu, 12 Nov 2026 13:32:22 -0700 [thread overview]
Message-ID: <20261112203227.289379-17-zide.chen@intel.com> (raw)
In-Reply-To: <20261112203227.289379-1-zide.chen@intel.com>
PerfMon v5 adds a fixed-counter support bitmap in CPUID.0AH:ECX.
This is a superset of EDX[4:0] which indicates the contiguous
counters starting from 0. For backward compatibility, it's recommended
to use the following to determine if a fixed counter is supported:
FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i);
Populate CPUID.0AH:ECX with kvm_pmu_cap.fixed_cntr_mask64 when KVM
supports PerfMon v5, and in intel_pmu_refresh(), incorporate the
guest's ECX bits into fixed_mask for PerfMon v5+ guests.
Originally-by: Yang Weijiang <weijiang.yang@intel.com>
Signed-off-by: Zide Chen <zide.chen@intel.com>
---
v4:
- Check pmu->version directly instead of checking both kvm_pmu_cap and
pmu version, as pmu->version is now clamped. (Yosry, Sean)
- Merge the blanket masking into the fixed_mask assignment. (Yosry)
v3:
- Remove '&' when populating entry->ecx. (Jim)
---
arch/x86/kvm/cpuid.c | 5 ++++-
arch/x86/kvm/vmx/pmu_intel.c | 3 +++
2 files changed, 7 insertions(+), 1 deletion(-)
diff --git a/arch/x86/kvm/cpuid.c b/arch/x86/kvm/cpuid.c
index 427871ec365f..2a4530d000fc 100644
--- a/arch/x86/kvm/cpuid.c
+++ b/arch/x86/kvm/cpuid.c
@@ -1554,7 +1554,10 @@ static inline int __do_cpuid_func(struct kvm_cpuid_array *array, u32 function)
entry->eax = eax.full;
entry->ebx = kvm_pmu_cap.events_mask;
- entry->ecx = 0;
+ if (kvm_pmu_cap.version >= 5)
+ entry->ecx = (u32)kvm_pmu_cap.fixed_cntr_mask64;
+ else
+ entry->ecx = 0;
entry->edx = edx.full;
break;
}
diff --git a/arch/x86/kvm/vmx/pmu_intel.c b/arch/x86/kvm/vmx/pmu_intel.c
index 0be9956810ae..d259b66abac8 100644
--- a/arch/x86/kvm/vmx/pmu_intel.c
+++ b/arch/x86/kvm/vmx/pmu_intel.c
@@ -593,7 +593,10 @@ static void intel_pmu_refresh(struct kvm_vcpu *vcpu)
find_first_zero_bit(kvm_pmu_cap.fixed_cntr_mask,
KVM_MAX_NR_FIXED_COUNTERS));
+ /* FxCtr[i]_is_supported := ECX[i] || (EDX[4:0] > i) */
fixed_mask = BIT_ULL(nr_fixed_counters) - 1;
+ if (pmu->version >= 5)
+ fixed_mask |= (entry->ecx & kvm_pmu_cap.fixed_cntr_mask64);
/*
* CPUID.0AH:EAX[15:8] can only enumerate contiguous counters. Clamp the
--
2.56.1
next prev parent reply other threads:[~2026-11-12 20:43 UTC|newest]
Thread overview: 22+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-12 20:32 [PATCH v4 00/21] KVM: x86/pmu: Add mediated vPMU PerfMon v5 support Zide Chen
2026-11-12 20:32 ` [PATCH v4 01/21] KVM: SVM: Drop counter MSR checks in amd_is_valid_msr() Zide Chen
2026-11-12 20:32 ` [PATCH v4 02/21] KVM: x86/pmu: Remove redundant Perf Global Status MSR bit definitions Zide Chen
2026-11-12 20:32 ` [PATCH v4 03/21] KVM: x86/pmu: Rename all_valid_pmc_idx to pmc_exists Zide Chen
2026-11-12 20:32 ` [PATCH v4 04/21] KVM: x86/pmu: Rename reserved_bits to eventsel_rsvd in kvm_pmu Zide Chen
2026-11-12 20:32 ` [PATCH v4 05/21] KVM: x86/pmu: Use pmc_exists in PMC lookup helpers Zide Chen
2026-11-12 20:32 ` [PATCH v4 06/21] KVM: x86/pmu: Drop nr_arch_{gp,fixed}_counters from kvm_pmu Zide Chen
2026-11-12 20:32 ` [PATCH v4 07/21] KVM: x86/pmu: Expose kvm_host_pmu to vendor modules Zide Chen
2026-11-12 20:32 ` [PATCH v4 08/21] perf/x86: Plumb counter bitmap from x86_pmu to x86_pmu_cap Zide Chen
2026-11-12 20:32 ` [PATCH v4 09/21] KVM: x86/pmu: Switch to bitmask-based KVM PMU capabilities Zide Chen
2026-11-12 20:32 ` [PATCH v4 10/21] perf/x86: Remove num_counters_{gp,fixed} from x86_pmu_capability Zide Chen
2026-11-12 20:32 ` [PATCH v4 11/21] KVM: x86/pmu: Document GLOBAL_STATUS_RESET passthrough erratum Zide Chen
2026-11-12 20:32 ` [PATCH v4 12/21] KVM: x86/pmu: Mark CondChgd reserved in global_status_rsvd Zide Chen
2026-11-12 20:32 ` [PATCH v4 13/21] KVM: x86/pmu: Emulate IA32_PERF_GLOBAL_STATUS_SET MSR Zide Chen
2026-11-12 20:32 ` [PATCH v4 14/21] KVM: x86/pmu: Emulate IA32_PERF_GLOBAL_INUSE MSR Zide Chen
2026-11-12 20:32 ` [PATCH v4 15/21] KVM: x86/pmu: Clamp pmu->version to kvm_pmu_cap.version Zide Chen
2026-11-12 20:32 ` Zide Chen [this message]
2026-11-12 20:32 ` [PATCH v4 17/21] KVM: x86/pmu: Factor out fixed counter control bit calculation Zide Chen
2026-11-12 20:32 ` [PATCH v4 18/21] KVM: x86/pmu: Mask only OS/USR bits when filtering fixed counters Zide Chen
2026-11-12 20:32 ` [PATCH v4 19/21] KVM: x86/pmu: Ignore AnyThread bit if CPUID.0AH:EDX[15] is set Zide Chen
2026-11-12 20:32 ` [PATCH v4 20/21] KVM: x86/pmu: Advertise PerfMon version 5 on Intel hosts Zide Chen
2026-11-12 20:32 ` [PATCH v4 21/21] KVM: selftests: Support fixed counters bitmap in pmu_counters_test Zide Chen
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