* [PATCH v1 1/6] arm64: cpufeature: Remove Neoverse-V3/AE from the BBML3 allow list
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
@ 2026-11-13 14:50 ` Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 2/6] arm64: cpufeature: Remove Cortex-X4 " Ryan Roberts
` (4 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ryan Roberts @ 2026-11-13 14:50 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Linu Cherian
Cc: Ryan Roberts, linux-arm-kernel, linux-kernel, stable
Neoverse-V3 and Neoverse-V3AE erratum 3053180 can cause a load or store
to livelock when mapping size changes without break-before-make or when
contiguous hints are programmed inconsistently.
The erratum was previously reported as fixed in r0p2. On that basis,
commit 5aa4b625762e ("arm64: Add BBM Level 2 cpu feature") allowed
Neoverse-V3 from r0p2, and commit 8fca3852e33d ("arm64: cpufeature: add
Neoverse-V3AE to BBML2 allow list") did the same for Neoverse-V3AE.
The updated SDENs, MP168 v11 for Neoverse-V3 and MP172 v12 for
Neoverse-V3AE, dated 9 June 2026, list r0p0, r0p1 and r0p2 as affected
and the erratum as open. There is no fixed revision on which to base
either allow-list entry.
Remove both entries so these CPUs observe break-before-make, and record
the workaround in the silicon errata registry.
Cc: stable@vger.kernel.org
Link: https://support.arm.com/documentation/109231/11-0/?lang=en
Link: https://support.arm.com/documentation/109704/12-0/?lang=en
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
Documentation/arch/arm64/silicon-errata.rst | 4 ++++
arch/arm64/kernel/cpufeature.c | 2 --
2 files changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index afe109afe692..9ad965d3e1ea 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -243,10 +243,14 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V2 | #4193787 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V3 | #3053180 | N/A |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3 | #4193784 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V3AE | #3053180 | N/A |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 |
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 34c5c03c0c9b..b15619690f42 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2012,8 +2012,6 @@ bool cpu_supports_bbml3(void)
/* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */
static const struct midr_range supports_bbml3_list[] = {
MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
- MIDR_REV_RANGE(MIDR_NEOVERSE_V3, 0, 2, 0xf),
- MIDR_REV_RANGE(MIDR_NEOVERSE_V3AE, 0, 2, 0xf),
MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
MIDR_ALL_VERSIONS(MIDR_NVIDIA_RIGEL),
MIDR_ALL_VERSIONS(MIDR_AMPERE1),
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v1 2/6] arm64: cpufeature: Remove Cortex-X4 from the BBML3 allow list
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 1/6] arm64: cpufeature: Remove Neoverse-V3/AE from the BBML3 allow list Ryan Roberts
@ 2026-11-13 14:50 ` Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 3/6] arm64: cputype: Add Cortex-A320 definitions Ryan Roberts
` (3 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ryan Roberts @ 2026-11-13 14:50 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Linu Cherian
Cc: Ryan Roberts, linux-arm-kernel, linux-kernel, stable
Cortex-X4 erratum 3043263 can cause a load or store to livelock when
mapping size changes without break-before-make or when contiguous hints
are programmed inconsistently.
The erratum was previously reported as fixed in r0p3. On that basis,
commit 5aa4b625762e ("arm64: Add BBM Level 2 cpu feature") added
Cortex-X4 from r0p3.
The updated Cortex-X4 SDEN v13, dated 18 June 2026, lists r0p0, r0p1,
r0p2 and r0p3 as affected and the erratum as open.
Remove the entry so Cortex-X4 observes break-before-make, and record the
workaround in the silicon errata registry.
Cc: stable@vger.kernel.org
Link: https://support.arm.com/documentation/109148/13-0/?lang=en
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
Documentation/arch/arm64/silicon-errata.rst | 2 ++
arch/arm64/kernel/cpufeature.c | 1 -
2 files changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 9ad965d3e1ea..9d6d13045a55 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -201,6 +201,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X3 | #4193786 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X4 | #3043263 | N/A |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X4 | #4118414 | ARM64_ERRATUM_4118414 |
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index b15619690f42..8819652a67ed 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2011,7 +2011,6 @@ bool cpu_supports_bbml3(void)
{
/* CPUs that support BBML3 but dont advertise through ID_AA64MMFR2_EL1 */
static const struct midr_range supports_bbml3_list[] = {
- MIDR_REV_RANGE(MIDR_CORTEX_X4, 0, 3, 0xf),
MIDR_ALL_VERSIONS(MIDR_NVIDIA_OLYMPUS),
MIDR_ALL_VERSIONS(MIDR_NVIDIA_RIGEL),
MIDR_ALL_VERSIONS(MIDR_AMPERE1),
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v1 3/6] arm64: cputype: Add Cortex-A320 definitions
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 1/6] arm64: cpufeature: Remove Neoverse-V3/AE from the BBML3 allow list Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 2/6] arm64: cpufeature: Remove Cortex-X4 " Ryan Roberts
@ 2026-11-13 14:50 ` Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 4/6] arm64: cputype: Add C2-Ultra definitions Ryan Roberts
` (2 subsequent siblings)
5 siblings, 0 replies; 7+ messages in thread
From: Ryan Roberts @ 2026-11-13 14:50 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Linu Cherian
Cc: Ryan Roberts, linux-arm-kernel, linux-kernel
Add the Cortex-A320 part number and MIDR definition. The MIDR_EL1
description in the Cortex-A320 Technical Reference Manual specifies
implementer 0x41 and part number 0xd8f.
These definitions will be used to identify Cortex-A320 in the BBML3
allow list.
Link: https://support.arm.com/documentation/109551/0002?lang=en&rev=0002-04
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index 6002d1d5f55f..abff1ba1c305 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -103,6 +103,7 @@
#define ARM_CPU_PART_C1_NANO 0xD8A
#define ARM_CPU_PART_C1_PRO 0xD8B
#define ARM_CPU_PART_C1_PREMIUM 0xD90
+#define ARM_CPU_PART_CORTEX_A320 0xD8F
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@@ -200,6 +201,7 @@
#define MIDR_C1_NANO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_NANO)
#define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
#define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
+#define MIDR_CORTEX_A320 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A320)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v1 4/6] arm64: cputype: Add C2-Ultra definitions
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
` (2 preceding siblings ...)
2026-11-13 14:50 ` [PATCH v1 3/6] arm64: cputype: Add Cortex-A320 definitions Ryan Roberts
@ 2026-11-13 14:50 ` Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 5/6] arm64: cpufeature: Track BBML3 exclusions with erratum options Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 6/6] arm64: cpufeature: Enable BBML3 on Cortex-A320, A520 and A720 Ryan Roberts
5 siblings, 0 replies; 7+ messages in thread
From: Ryan Roberts @ 2026-11-13 14:50 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Linu Cherian
Cc: Ryan Roberts, linux-arm-kernel, linux-kernel
Add the C2-Ultra part number and MIDR definition. The MIDR_EL1
description in the C2-Ultra Technical Reference Manual specifies
implementer 0x41 and part number 0xd96.
These definitions will be used to identify C2-Ultra in the BBML3 allow
list.
Link: https://support.arm.com/documentation/109736/0001?lang=en&rev=0001-05
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
arch/arm64/include/asm/cputype.h | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm64/include/asm/cputype.h b/arch/arm64/include/asm/cputype.h
index abff1ba1c305..55493e01009e 100644
--- a/arch/arm64/include/asm/cputype.h
+++ b/arch/arm64/include/asm/cputype.h
@@ -104,6 +104,7 @@
#define ARM_CPU_PART_C1_PRO 0xD8B
#define ARM_CPU_PART_C1_PREMIUM 0xD90
#define ARM_CPU_PART_CORTEX_A320 0xD8F
+#define ARM_CPU_PART_C2_ULTRA 0xD96
#define APM_CPU_PART_XGENE 0x000
#define APM_CPU_VAR_POTENZA 0x00
@@ -202,6 +203,7 @@
#define MIDR_C1_PRO MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PRO)
#define MIDR_C1_PREMIUM MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C1_PREMIUM)
#define MIDR_CORTEX_A320 MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_CORTEX_A320)
+#define MIDR_C2_ULTRA MIDR_CPU_MODEL(ARM_CPU_IMP_ARM, ARM_CPU_PART_C2_ULTRA)
#define MIDR_THUNDERX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX)
#define MIDR_THUNDERX_81XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_81XX)
#define MIDR_THUNDERX_83XX MIDR_CPU_MODEL(ARM_CPU_IMP_CAVIUM, CAVIUM_CPU_PART_THUNDERX_83XX)
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v1 5/6] arm64: cpufeature: Track BBML3 exclusions with erratum options
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
` (3 preceding siblings ...)
2026-11-13 14:50 ` [PATCH v1 4/6] arm64: cputype: Add C2-Ultra definitions Ryan Roberts
@ 2026-11-13 14:50 ` Ryan Roberts
2026-11-13 14:50 ` [PATCH v1 6/6] arm64: cpufeature: Enable BBML3 on Cortex-A320, A520 and A720 Ryan Roberts
5 siblings, 0 replies; 7+ messages in thread
From: Ryan Roberts @ 2026-11-13 14:50 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Linu Cherian
Cc: Ryan Roberts, linux-arm-kernel, linux-kernel
Several CPUs implementing the BBML3 no-abort semantics advertise only
BBML2, but cannot safely use those semantics because of hardware errata.
Omitting their MIDRs from the allow list hides the reason for the
exclusion and makes the relevant workarounds difficult to track.
Add a default-enabled Kconfig option for each of the following errata,
and include the affected CPUs in the BBML3 allow list only when the
corresponding workaround is disabled:
3043240 Cortex-X925
3043263 Cortex-X4
3053180 Neoverse-V3 and Neoverse-V3AE
3683289 C1-Ultra and C1-Premium
3696239 Cortex-X3
3696242 Neoverse-V2
3696244 Cortex-A710 and Cortex-X2
3696250 Neoverse-N2
3696285 Neoverse-V1
4196850 C2-Ultra
These errata can cause a load or store to livelock when mapping size
changes without break-before-make or contiguous hints are inconsistent.
For CPUs with no documented fixed revision, exclude all revisions while
the workaround is enabled.
Preserve the C1-Ultra and C1-Premium entries from r1p1, where erratum
3683289 is fixed. Disabling that workaround additionally allows their
earlier revisions.
Note that Cortex-A510 advertises BBML2 and is not subject to any errata,
but it can generate conflict aborts, and so does not meet the
requirements of BBML3. It is therefore not included in the list.
Link: https://support.arm.com/documentation/109180/13-0/?lang=en
Link: https://support.arm.com/documentation/111077/10-0/?lang=en
Link: https://support.arm.com/documentation/111078/10-0/?lang=en
Link: https://support.arm.com/documentation/111287/10-0/?lang=en
Link: https://support.arm.com/documentation/SDEN-2055130/18-0?lang=en&rev=18.0
Link: https://support.arm.com/documentation/SDEN-2332927/13-0?lang=en&rev=13.0
Link: https://support.arm.com/documentation/SDEN-1775101/23-0?lang=en&rev=23.0
Link: https://support.arm.com/documentation/SDEN-1775100/23-0?lang=en&rev=23.0
Link: https://support.arm.com/documentation/SDEN-1982442/21-0?lang=en&rev=21.0
Link: https://support.arm.com/documentation/SDEN-1401781/23-0?lang=en&rev=23.0
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
Documentation/arch/arm64/silicon-errata.rst | 26 +++-
arch/arm64/Kconfig | 163 ++++++++++++++++++++
arch/arm64/kernel/cpufeature.c | 37 ++++-
3 files changed, 220 insertions(+), 6 deletions(-)
diff --git a/Documentation/arch/arm64/silicon-errata.rst b/Documentation/arch/arm64/silicon-errata.rst
index 9d6d13045a55..a515d01266ae 100644
--- a/Documentation/arch/arm64/silicon-errata.rst
+++ b/Documentation/arch/arm64/silicon-errata.rst
@@ -159,6 +159,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A78C | #4193794 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-A710 | #3696244 | ARM64_ERRATUM_3696244 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-A710 | #2054223 | ARM64_ERRATUM_2054223 |
@@ -189,6 +191,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X1C | #4193792 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X2 | #3696244 | ARM64_ERRATUM_3696244 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #2119858 | ARM64_ERRATUM_2119858 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #2224489 | ARM64_ERRATUM_2224489 |
@@ -197,16 +201,20 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X2 | #4193788 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X3 | #3696239 | ARM64_ERRATUM_3696239 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X3 | #3324335 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X3 | #4193786 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
-| ARM | Cortex-X4 | #3043263 | N/A |
+| ARM | Cortex-X4 | #3043263 | ARM64_ERRATUM_3043263 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X4 | #3194386 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X4 | #4118414 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Cortex-X925 | #3043240 | ARM64_ERRATUM_3043240 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X925 | #3324334 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Cortex-X925 | #4193781 | ARM64_ERRATUM_4118414 |
@@ -223,6 +231,8 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N1 | #4193800 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-N2 | #3696250 | ARM64_ERRATUM_3696250 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2139208 | ARM64_ERRATUM_2139208 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N2 | #2067961 | ARM64_ERRATUM_2067961 |
@@ -235,38 +245,44 @@ stable kernels.
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-N3 | #3456111 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V1 | #3696285 | ARM64_ERRATUM_3696285 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V1 | #1619801 | N/A |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V1 | #3324341 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V1 | #4193790 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | Neoverse-V2 | #3696242 | ARM64_ERRATUM_3696242 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V2 | #3324336 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V2 | #4193787 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
-| ARM | Neoverse-V3 | #3053180 | N/A |
+| ARM | Neoverse-V3 | #3053180 | ARM64_ERRATUM_3053180 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3 | #3312417 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3 | #4193784 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
-| ARM | Neoverse-V3AE | #3053180 | N/A |
+| ARM | Neoverse-V3AE | #3053180 | ARM64_ERRATUM_3053180 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3AE | #3312417 | ARM64_ERRATUM_3194386 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | Neoverse-V3AE | #4193784 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
-| ARM | C1-Premium | #3683289 | N/A |
+| ARM | C1-Premium | #3683289 | ARM64_ERRATUM_3683289 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | C1-Premium | #4193780 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | C1-Pro | #4193714 | ARM64_ERRATUM_4193714 |
+----------------+-----------------+-----------------+-----------------------------+
-| ARM | C1-Ultra | #3683289 | N/A |
+| ARM | C1-Ultra | #3683289 | ARM64_ERRATUM_3683289 |
+----------------+-----------------+-----------------+-----------------------------+
| ARM | C1-Ultra | #4193780 | ARM64_ERRATUM_4118414 |
+----------------+-----------------+-----------------+-----------------------------+
+| ARM | C2-Ultra | #4196850 | ARM64_ERRATUM_4196850 |
++----------------+-----------------+-----------------+-----------------------------+
| ARM | MMU-500 | #562869, | ARM_SMMU_MMU_500_CPRE_ERRATA|
| | | #841119, | |
| | | #826419, | |
diff --git a/arch/arm64/Kconfig b/arch/arm64/Kconfig
index 1075bc661833..79c92805c694 100644
--- a/arch/arm64/Kconfig
+++ b/arch/arm64/Kconfig
@@ -1248,6 +1248,169 @@ config ARM64_ERRATUM_4118414
If unsure, say Y.
+config ARM64_ERRATUM_3043240
+ bool "Cortex-X925: 3043240: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Cortex-X925 erratum 3043240,
+ which affects r0p0, r0p1 and r0p2. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Cortex-X925 from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3043263
+ bool "Cortex-X4: 3043263: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Cortex-X4 erratum 3043263,
+ which affects r0p0, r0p1, r0p2 and r0p3. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Cortex-X4 from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3053180
+ bool "Neoverse-V3/V3AE: 3053180: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Neoverse-V3 and Neoverse-V3AE
+ erratum 3053180, which affects r0p0, r0p1 and r0p2. Contrary to earlier
+ errata notices, r0p2 is affected. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Neoverse-V3 and
+ Neoverse-V3AE from the BBML3 allow list, so Linux uses break-before-make.
+ Disabling this option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3683289
+ bool "C1-Ultra/Premium: 3683289: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm C1-Ultra and C1-Premium erratum
+ 3683289, which affects r0p0 and r1p0 and is fixed in r1p1.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding revisions earlier than r1p1 from the
+ BBML3 allow list, so Linux uses break-before-make on affected CPUs.
+ Disabling this option allows BBML3 to be used on all revisions.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3696239
+ bool "Cortex-X3: 3696239: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Cortex-X3 erratum 3696239,
+ which affects r0p0, r1p0, r1p1 and r1p2. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Cortex-X3 from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3696242
+ bool "Neoverse-V2: 3696242: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Neoverse-V2 erratum 3696242,
+ which affects r0p0, r0p1 and r0p2. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Neoverse-V2 from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3696244
+ bool "Cortex-A710/X2: 3696244: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Cortex-A710 and Cortex-X2
+ erratum 3696244, which affects r0p0, r1p0, r2p0 and r2p1. No fixed
+ revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Cortex-A710 and
+ Cortex-X2 from the BBML3 allow list, so Linux uses break-before-make.
+ Disabling this option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3696250
+ bool "Neoverse-N2: 3696250: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Neoverse-N2 erratum 3696250,
+ which affects r0p0, r0p1, r0p2 and r0p3. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Neoverse-N2 from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_3696285
+ bool "Neoverse-V1: 3696285: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm Neoverse-V1 erratum 3696285,
+ which affects r0p0, r1p0, r1p1 and r1p2. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of Neoverse-V1 from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
+config ARM64_ERRATUM_4196850
+ bool "C2-Ultra: 4196850: BBM-related livelock"
+ default y
+ help
+ This option adds the workaround for Arm C2-Ultra erratum 4196850,
+ which affects r0p0 and r0p1. Contrary to earlier errata notices, r0p1
+ is affected. No fixed revision is known.
+
+ Changing mapping size without break-before-make or using inconsistent
+ contiguous hints can cause a load or store to livelock.
+
+ Work around this by excluding all revisions of C2-Ultra from the
+ BBML3 allow list, so Linux uses break-before-make. Disabling this
+ option allows BBML3 to be used on these CPUs.
+
+ If unsure, say Y.
+
config CAVIUM_ERRATUM_22375
bool "Cavium erratum 22375, 24313"
default y
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index 8819652a67ed..aa6f4c8c1052 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2016,15 +2016,50 @@ bool cpu_supports_bbml3(void)
MIDR_ALL_VERSIONS(MIDR_AMPERE1),
MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
+#ifndef CONFIG_ARM64_ERRATUM_3696244
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
+#endif
MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
+#ifndef CONFIG_ARM64_ERRATUM_3696244
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X2),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_3696239
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X3),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_3043263
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X4),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_3043240
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_X925),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_3696250
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N2),
+#endif
MIDR_ALL_VERSIONS(MIDR_NEOVERSE_N3),
+#ifndef CONFIG_ARM64_ERRATUM_3696285
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V1),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_3696242
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V2),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_3053180
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3),
+ MIDR_ALL_VERSIONS(MIDR_NEOVERSE_V3AE),
+#endif
MIDR_ALL_VERSIONS(MIDR_C1_NANO),
MIDR_ALL_VERSIONS(MIDR_C1_PRO),
- /* Erratum 3683289 fixed in r1p1 */
+#ifndef CONFIG_ARM64_ERRATUM_3683289
+ MIDR_ALL_VERSIONS(MIDR_C1_ULTRA),
+ MIDR_ALL_VERSIONS(MIDR_C1_PREMIUM),
+#else
MIDR_RANGE(MIDR_C1_ULTRA, 1, 1, 0xf, 0xf),
MIDR_RANGE(MIDR_C1_PREMIUM, 1, 1, 0xf, 0xf),
+#endif
+#ifndef CONFIG_ARM64_ERRATUM_4196850
+ MIDR_ALL_VERSIONS(MIDR_C2_ULTRA),
+#endif
{}
};
u64 mmfr2 = __read_sysreg_by_encoding(SYS_ID_AA64MMFR2_EL1);
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread* [PATCH v1 6/6] arm64: cpufeature: Enable BBML3 on Cortex-A320, A520 and A720
2026-11-13 14:50 [PATCH v1 0/6] arm64: BBML3 errata workarounds and cleanup Ryan Roberts
` (4 preceding siblings ...)
2026-11-13 14:50 ` [PATCH v1 5/6] arm64: cpufeature: Track BBML3 exclusions with erratum options Ryan Roberts
@ 2026-11-13 14:50 ` Ryan Roberts
5 siblings, 0 replies; 7+ messages in thread
From: Ryan Roberts @ 2026-11-13 14:50 UTC (permalink / raw)
To: Catalin Marinas, Will Deacon, Mark Rutland, Linu Cherian
Cc: Ryan Roberts, linux-arm-kernel, linux-kernel
Cortex-A320, Cortex-A520 and Cortex-A720 advertise BBML2 and are known
not to raise conflict aborts for mapping-granularity changes. They can
therefore use the BBML3 semantics, but their MIDRs are missing from the
allow list.
Commit a7ac60414475 ("arm64: cpufeature: Extend bbml2_noabort support
list") named A520(AE) and A720(AE), but added only the AE MIDRs. The
non-AE CPUs have distinct MIDRs and need their own entries. Cortex-A320
can now be identified using its new MIDR definition.
Add all revisions of these three CPUs to the allow list. The reviewed
SDENs identify no BBML3 exclusion erratum for them.
Cortex-A510 remains excluded because it can raise conflict aborts.
Link: https://support.arm.com/documentation/SDEN-2877630/0000?lang=en&rev=0000-06
Link: https://support.arm.com/documentation/SDEN-2444153/0000?lang=en&rev=0000-12
Link: https://support.arm.com/documentation/SDEN-2439421/0000?lang=en&rev=0000-17
Signed-off-by: Ryan Roberts <ryan.roberts@arm.com>
---
arch/arm64/kernel/cpufeature.c | 3 +++
1 file changed, 3 insertions(+)
diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
index aa6f4c8c1052..de2d2bd686d8 100644
--- a/arch/arm64/kernel/cpufeature.c
+++ b/arch/arm64/kernel/cpufeature.c
@@ -2015,11 +2015,14 @@ bool cpu_supports_bbml3(void)
MIDR_ALL_VERSIONS(MIDR_NVIDIA_RIGEL),
MIDR_ALL_VERSIONS(MIDR_AMPERE1),
MIDR_ALL_VERSIONS(MIDR_AMPERE1A),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A320),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A520),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A520AE),
#ifndef CONFIG_ARM64_ERRATUM_3696244
MIDR_ALL_VERSIONS(MIDR_CORTEX_A710),
#endif
MIDR_ALL_VERSIONS(MIDR_CORTEX_A715),
+ MIDR_ALL_VERSIONS(MIDR_CORTEX_A720),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A720AE),
MIDR_ALL_VERSIONS(MIDR_CORTEX_A725),
#ifndef CONFIG_ARM64_ERRATUM_3696244
--
2.43.0
^ permalink raw reply [flat|nested] 7+ messages in thread