From: Ian Rogers <irogers@google.com>
To: Peter Zijlstra <peterz@infradead.org>,
Ingo Molnar <mingo@redhat.com>,
Arnaldo Carvalho de Melo <acme@kernel.org>,
Namhyung Kim <namhyung@kernel.org>
Cc: Jiri Olsa <jolsa@kernel.org>,
Adrian Hunter <adrian.hunter@intel.com>,
James Clark <james.clark@linaro.org>,
Kan Liang <kan.liang@linux.intel.com>,
linux-perf-users@vger.kernel.org, linux-kernel@vger.kernel.org,
Ian Rogers <irogers@google.com>
Subject: [PATCH 02/10] perf jevents: Sort BigCString entries alphabetically
Date: Fri, 13 Nov 2026 13:08:14 -0800 [thread overview]
Message-ID: <20261113210822.3112700-3-irogers@google.com> (raw)
In-Reply-To: <20261113210822.3112700-1-irogers@google.com>
Currently BigCString partitions non-metric event strings before metric
and metricgroup strings, and orders deduplicated entries within each
partition by first-seen insertion order (insert_point). Because strings
shared across multiple CPU models stay at their earliest insertion
position while model-unique strings are appended later, later models are
already fragmented across big_c_string, and identically prefixed event
and metric definitions from different models are scattered far apart.
Drop insert_number/insert_point so non-folded BigCString entries are
still partitioned with event strings before metric strings, and sorted
lexicographically by their raw UTF-8 byte sequence (which starts with
the NUL-terminated event or metric name) within each partition. Grouping
identically prefixed event names, event encodings, descriptions, and
metric expressions adjacent to one another prepares big_c_string for
block-indexed string compression (splitting big_c_string into
independently compressed ~8 KiB blocks decompressed on demand by block
index and intra-block byte offset), shrinking the compressed blocks by
~20-23%.
Regenerate empty-pmu-events.c for the updated string offsets.
Signed-off-by: Ian Rogers <irogers@google.com>
---
tools/perf/pmu-events/empty-pmu-events.c | 7700 +++++++++++-----------
tools/perf/pmu-events/jevents.py | 10 +-
2 files changed, 3852 insertions(+), 3858 deletions(-)
diff --git a/tools/perf/pmu-events/empty-pmu-events.c b/tools/perf/pmu-events/empty-pmu-events.c
index 7df1552403e7..c0023687e3dd 100644
--- a/tools/perf/pmu-events/empty-pmu-events.c
+++ b/tools/perf/pmu-events/empty-pmu-events.c
@@ -20,5166 +20,5166 @@ struct pmu_table_entry {
/* clang-format off */
static const char *const big_c_string =
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+/* offset=13959 */
+"bus-cycles\000legacy hardware\000Bus cycles, which can be different from total cycles\000legacy-hardware-config=6\000\00000\000\000\000\000\000"
+/* offset=14072 */
+"cache-misses\000legacy hardware\000Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in conjunction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate cache miss rates\000legacy-hardware-config=3\000\00000\000\000\000\000\000"
+/* offset=14315 */
+"cache-references\000legacy hardware\000Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending on your CPU. This may include prefetches and coherency messages; again this depends on the design of your CPU\000legacy-hardware-config=2\000\00000\000\000\000\000\000"
+/* offset=14585 */
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+/* offset=14688 */
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+/* offset=14789 */
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+/* offset=14903 */
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+/* offset=14989 */
+"cpu-cycles\000legacy hardware\000Total cycles. Be wary of what happens during CPU frequency scaling [This event is an alias of cycles]\000legacy-hardware-config=0\000\00000\000\000\000\000\000"
+/* offset=15151 */
+"cpu-migrations\000software\000Number of times a process has migrated to a new CPU [This event is an alias of migrations]\000config=4\000\00000\000\000\000\000\000"
+/* offset=15283 */
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+/* offset=15384 */
+"cycles\000legacy hardware\000Total cycles. Be wary of what happens during CPU frequency scaling [This event is an alias of cpu-cycles]\000legacy-hardware-config=0\000\00000\000\000\000\000\000"
+/* offset=15546 */
"d-tlb\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\00010\000\000\000\000\000"
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"d-tlb-load\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\00010\000\000\000\000\000"
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"d-tlb-load-access\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\00010\000\000\000\000\000"
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"d-tlb-load-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x10003\000\00010\000\000\000\000\000"
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"d-tlb-loads\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\00010\000\000\000\000\000"
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"d-tlb-loads-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x10003\000\00010\000\000\000\000\000"
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+/* offset=37292 */
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"i-tlb\000legacy cache\000Instruction TLB read accesses\000legacy-cache-config=4\000\00010\000\000\000\000\000"
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"i-tlb-load-access\000legacy cache\000Instruction TLB read accesses\000legacy-cache-config=4\000\00010\000\000\000\000\000"
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"i-tlb-load-miss\000legacy cache\000Instruction TLB read misses\000legacy-cache-config=0x10004\000\00010\000\000\000\000\000"
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"i-tlb-loads-access\000legacy cache\000Instruction TLB read accesses\000legacy-cache-config=4\000\00010\000\000\000\000\000"
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"i-tlb-loads-miss\000legacy cache\000Instruction TLB read misses\000legacy-cache-config=0x10004\000\00010\000\000\000\000\000"
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"i-tlb-read-access\000legacy cache\000Instruction TLB read accesses\000legacy-cache-config=4\000\00010\000\000\000\000\000"
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"i-tlb-read-miss\000legacy cache\000Instruction TLB read misses\000legacy-cache-config=0x10004\000\00010\000\000\000\000\000"
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+/* offset=39643 */
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+/* offset=39732 */
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+/* offset=39905 */
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+/* offset=40058 */
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"instruction-tlb\000legacy cache\000Instruction TLB read accesses\000legacy-cache-config=4\000\00010\000\000\000\000\000"
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-"node-write-reference\000legacy cache\000Local memory write accesses\000legacy-cache-config=0x106\000\00010\000\000\000\000\000"
-/* offset=117588 */
-"node-write-ops\000legacy cache\000Local memory write accesses\000legacy-cache-config=0x106\000\00010\000\000\000\000\000"
-/* offset=117678 */
+/* offset=124787 */
"node-write-access\000legacy cache\000Local memory write accesses\000legacy-cache-config=0x106\000\00010\000\000\000\000\000"
-/* offset=117771 */
-"node-write-misses\000legacy cache\000Local memory write misses\000legacy-cache-config=0x10106\000\00010\000\000\000\000\000"
-/* offset=117864 */
+/* offset=124880 */
"node-write-miss\000legacy cache\000Local memory write misses\000legacy-cache-config=0x10106\000\00010\000\000\000\000\000"
-/* offset=117955 */
-"node-prefetch\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118047 */
-"node-prefetch-refs\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118144 */
-"node-prefetch-reference\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118246 */
-"node-prefetch-ops\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118342 */
-"node-prefetch-access\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118441 */
-"node-prefetch-misses\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00000\000\000\000\000\000"
-/* offset=118540 */
-"node-prefetch-miss\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=118637 */
-"node-prefetches\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00000\000\000\000\000\000"
-/* offset=118731 */
-"node-prefetches-refs\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118830 */
-"node-prefetches-reference\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=118934 */
-"node-prefetches-ops\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119032 */
-"node-prefetches-access\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119133 */
-"node-prefetches-misses\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=119234 */
-"node-prefetches-miss\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=119333 */
-"node-speculative-read\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119433 */
-"node-speculative-read-refs\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119538 */
-"node-speculative-read-reference\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119648 */
-"node-speculative-read-ops\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119752 */
-"node-speculative-read-access\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=119859 */
-"node-speculative-read-misses\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=119966 */
-"node-speculative-read-miss\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=120071 */
-"node-speculative-load\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=120171 */
-"node-speculative-load-refs\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=120276 */
-"node-speculative-load-reference\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=120386 */
-"node-speculative-load-ops\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=120490 */
-"node-speculative-load-access\000legacy cache\000Local memory prefetch accesses\000legacy-cache-config=0x206\000\00010\000\000\000\000\000"
-/* offset=120597 */
-"node-speculative-load-misses\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=120704 */
-"node-speculative-load-miss\000legacy cache\000Local memory prefetch misses\000legacy-cache-config=0x10206\000\00010\000\000\000\000\000"
-/* offset=120809 */
-"node-refs\000legacy cache\000Local memory read accesses\000legacy-cache-config=6\000\00010\000\000\000\000\000"
-/* offset=120889 */
-"node-reference\000legacy cache\000Local memory read accesses\000legacy-cache-config=6\000\00010\000\000\000\000\000"
-/* offset=120974 */
-"node-ops\000legacy cache\000Local memory read accesses\000legacy-cache-config=6\000\00010\000\000\000\000\000"
-/* offset=121053 */
-"node-access\000legacy cache\000Local memory read accesses\000legacy-cache-config=6\000\00010\000\000\000\000\000"
-/* offset=121135 */
-"node-misses\000legacy cache\000Local memory read misses\000legacy-cache-config=0x10006\000\00010\000\000\000\000\000"
-/* offset=121221 */
-"node-miss\000legacy cache\000Local memory read misses\000legacy-cache-config=0x10006\000\00010\000\000\000\000\000"
-/* offset=121305 */
-"cpu-cycles\000legacy hardware\000Total cycles. Be wary of what happens during CPU frequency scaling [This event is an alias of cycles]\000legacy-hardware-config=0\000\00000\000\000\000\000\000"
-/* offset=121467 */
-"cycles\000legacy hardware\000Total cycles. Be wary of what happens during CPU frequency scaling [This event is an alias of cpu-cycles]\000legacy-hardware-config=0\000\00000\000\000\000\000\000"
-/* offset=121629 */
-"instructions\000legacy hardware\000Retired instructions. Be careful, these can be affected by various issues, most notably hardware interrupt counts\000legacy-hardware-config=1\000\00000\000\000\000\000\000"
-/* offset=121805 */
-"cache-references\000legacy hardware\000Cache accesses. Usually this indicates Last Level Cache accesses but this may vary depending on your CPU. This may include prefetches and coherency messages; again this depends on the design of your CPU\000legacy-hardware-config=2\000\00000\000\000\000\000\000"
-/* offset=122075 */
-"cache-misses\000legacy hardware\000Cache misses. Usually this indicates Last Level Cache misses; this is intended to be used in conjunction with the PERF_COUNT_HW_CACHE_REFERENCES event to calculate cache miss rates\000legacy-hardware-config=3\000\00000\000\000\000\000\000"
-/* offset=122318 */
-"branches\000legacy hardware\000Retired branch instructions [This event is an alias of branch-instructions]\000legacy-hardware-config=4\000\00000\000\000\000\000\000"
-/* offset=122452 */
-"branch-instructions\000legacy hardware\000Retired branch instructions [This event is an alias of branches]\000legacy-hardware-config=4\000\00000\000\000\000\000\000"
-/* offset=122586 */
-"branch-misses\000legacy hardware\000Mispredicted branch instructions\000legacy-hardware-config=5\000\00000\000\000\000\000\000"
-/* offset=122682 */
-"bus-cycles\000legacy hardware\000Bus cycles, which can be different from total cycles\000legacy-hardware-config=6\000\00000\000\000\000\000\000"
-/* offset=122795 */
-"stalled-cycles-frontend\000legacy hardware\000Stalled cycles during issue [This event is an alias of idle-cycles-frontend]\000legacy-hardware-config=7\000\00000\000\000\000\000\000"
-/* offset=122945 */
-"idle-cycles-frontend\000legacy hardware\000Stalled cycles during issue [This event is an alias of stalled-cycles-frontend]\000legacy-hardware-config=7\000\00000\000\000\000\000\000"
-/* offset=123095 */
-"stalled-cycles-backend\000legacy hardware\000Stalled cycles during retirement [This event is an alias of idle-cycles-backend]\000legacy-hardware-config=8\000\00000\000\000\000\000\000"
-/* offset=123248 */
-"idle-cycles-backend\000legacy hardware\000Stalled cycles during retirement [This event is an alias of stalled-cycles-backend]\000legacy-hardware-config=8\000\00000\000\000\000\000\000"
-/* offset=123401 */
-"ref-cycles\000legacy hardware\000Total cycles; not affected by CPU frequency scaling\000legacy-hardware-config=9\000\00000\000\000\000\000\000"
-/* offset=123513 */
-"software\000"
-/* offset=123522 */
-"cpu-clock\000software\000Per-CPU high-resolution timer based event\000config=0\000\000001e-6msec\000\000\000\000\000"
-/* offset=123608 */
-"task-clock\000software\000Per-task high-resolution timer based event\000config=1\000\000001e-6msec\000\000\000\000\000"
-/* offset=123696 */
-"faults\000software\000Number of page faults [This event is an alias of page-faults]\000config=2\000\00000\000\000\000\000\000"
-/* offset=123791 */
-"page-faults\000software\000Number of page faults [This event is an alias of faults]\000config=2\000\00000\000\000\000\000\000"
-/* offset=123886 */
-"context-switches\000software\000Number of context switches [This event is an alias of cs]\000config=3\000\00000\000\000\000\000\000"
-/* offset=123987 */
-"cs\000software\000Number of context switches [This event is an alias of context-switches]\000config=3\000\00000\000\000\000\000\000"
-/* offset=124088 */
-"cpu-migrations\000software\000Number of times a process has migrated to a new CPU [This event is an alias of migrations]\000config=4\000\00000\000\000\000\000\000"
-/* offset=124220 */
-"migrations\000software\000Number of times a process has migrated to a new CPU [This event is an alias of cpu-migrations]\000config=4\000\00000\000\000\000\000\000"
-/* offset=124352 */
-"minor-faults\000software\000Number of minor page faults. Minor faults don't require I/O to handle\000config=5\000\00000\000\000\000\000\000"
-/* offset=124461 */
-"major-faults\000software\000Number of major page faults. Major faults require I/O to handle\000config=6\000\00000\000\000\000\000\000"
-/* offset=124564 */
-"alignment-faults\000software\000Number of kernel handled memory alignment faults\000config=7\000\00000\000\000\000\000\000"
-/* offset=124656 */
-"emulation-faults\000software\000Number of kernel handled unimplemented instruction faults handled through emulation\000config=8\000\00000\000\000\000\000\000"
-/* offset=124783 */
-"dummy\000software\000A placeholder event that doesn't count anything\000config=9\000\00000\000\000\000\000\000"
-/* offset=124863 */
-"bpf-output\000software\000An event used by BPF programs to write to the perf ring buffer\000config=0xa\000\00000\000\000\000\000\000"
-/* offset=124965 */
-"cgroup-switches\000software\000Number of context switches to a task in a different cgroup\000config=0xb\000\00000\000\000\000\000\000"
-/* offset=125068 */
-"tool\000"
-/* offset=125073 */
-"duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000\00000\000\000\000\000\000"
-/* offset=125149 */
-"user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000\000\000\000"
-/* offset=125219 */
-"system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000\000\000\000"
-/* offset=125287 */
-"has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000\00000\000\000\000\000\000"
-/* offset=125363 */
+/* offset=124971 */
+"node-write-misses\000legacy cache\000Local memory write misses\000legacy-cache-config=0x10106\000\00010\000\000\000\000\000"
+/* offset=125064 */
+"node-write-ops\000legacy cache\000Local memory write accesses\000legacy-cache-config=0x106\000\00010\000\000\000\000\000"
+/* offset=125154 */
+"node-write-reference\000legacy cache\000Local memory write accesses\000legacy-cache-config=0x106\000\00010\000\000\000\000\000"
+/* offset=125250 */
+"node-write-refs\000legacy cache\000Local memory write accesses\000legacy-cache-config=0x106\000\00010\000\000\000\000\000"
+/* offset=125341 */
"num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with each thread being associated with a logical Linux CPU\000config=5\000\00000\000\000\000\000\000"
-/* offset=125508 */
+/* offset=125486 */
"num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPUs on a core\000config=6\000\00000\000\000\000\000\000"
-/* offset=125611 */
+/* offset=125589 */
"num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be multiple such CPUs on a core\000config=7\000\00000\000\000\000\000\000"
-/* offset=125728 */
+/* offset=125706 */
"num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000\00000\000\000\000\000\000"
-/* offset=125804 */
+/* offset=125782 */
"num_packages\000tool\000Number of packages. Each package has 1 or more die\000config=9\000\00000\000\000\000\000\000"
-/* offset=125890 */
+/* offset=125868 */
+"page-faults\000software\000Number of page faults [This event is an alias of faults]\000config=2\000\00000\000\000\000\000\000"
+/* offset=125963 */
+"ref-cycles\000legacy hardware\000Total cycles; not affected by CPU frequency scaling\000legacy-hardware-config=9\000\00000\000\000\000\000\000"
+/* offset=126075 */
+"segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\000\000\000\000"
+/* offset=126177 */
"slots\000tool\000Number of functional units that in parallel can execute parts of an instruction\000config=0xa\000\00000\000\000\000\000\000"
-/* offset=126000 */
+/* offset=126287 */
"smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enable otherwise 0\000config=0xb\000\00000\000\000\000\000\000"
-/* offset=126107 */
+/* offset=126394 */
+"software\000"
+/* offset=126403 */
+"stalled-cycles-backend\000legacy hardware\000Stalled cycles during retirement [This event is an alias of idle-cycles-backend]\000legacy-hardware-config=8\000\00000\000\000\000\000\000"
+/* offset=126556 */
+"stalled-cycles-frontend\000legacy hardware\000Stalled cycles during issue [This event is an alias of idle-cycles-frontend]\000legacy-hardware-config=7\000\00000\000\000\000\000\000"
+/* offset=126706 */
+"sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000\000\000"
+/* offset=126783 */
+"sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000\000\000"
+/* offset=126926 */
+"sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000\000\000"
+/* offset=127002 */
+"system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\000\000\000\000\000"
+/* offset=127070 */
"system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per second\000config=0xc\000\00000\000\000\000\000\000"
-/* offset=126206 */
-"core_wide\000tool\0001 if not SMT, if SMT are events being gathered on all SMT threads 1 otherwise 0\000config=0xd\000\00000\000\000\000\000\000"
-/* offset=126320 */
+/* offset=127169 */
"target_cpu\000tool\0001 if CPUs being analyzed, 0 if threads/processes\000config=0xe\000\00000\000\000\000\000\000"
-/* offset=126404 */
-"bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000\000\000\000"
-/* offset=126466 */
-"bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000\000\000\000"
-/* offset=126528 */
-"l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000\000\000\000Attributable Level 3 cache access, read\000"
-/* offset=126626 */
-"segment_reg_loads.any\000other\000Number of segment register loads\000event=6,period=200000,umask=0x80\000\00000\000\000\000\000\000"
-/* offset=126728 */
-"dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispatch for any reason\000event=9,period=200000,umask=0x20\000\00000\000\000\000\000\000"
-/* offset=126861 */
-"eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) transitions\000event=0x3a,period=200000\000\00000\000\000\000\000\000"
-/* offset=126979 */
-"hisi_sccl,ddrc\000"
-/* offset=126994 */
-"uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\000\000\000\000"
-/* offset=127064 */
-"uncore_cbox\000"
-/* offset=127076 */
+/* offset=127253 */
+"task-clock\000software\000Per-task high-resolution timer based event\000config=1\000\000001e-6msec\000\000\000\000\000"
+/* offset=127341 */
+"tool\000"
+/* offset=127346 */
"unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted from L3 Eviction which misses in some processor core\000event=0x22,umask=0x81\000\00000\000\000\000\000\000"
-/* offset=127230 */
-"event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000\000\000\000\000"
-/* offset=127284 */
-"event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000\000\000\000\000"
-/* offset=127342 */
-"hisi_sccl,l3c\000"
-/* offset=127356 */
+/* offset=127500 */
+"uncore_cbox\000"
+/* offset=127512 */
+"uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000\000\000\000\000\000"
+/* offset=127582 */
"uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\000\000\000\000\000"
-/* offset=127424 */
-"uncore_imc_free_running\000"
-/* offset=127448 */
-"uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000\000\000\000\000"
-/* offset=127528 */
+/* offset=127650 */
"uncore_imc\000"
-/* offset=127539 */
+/* offset=127661 */
"uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000\000\000\000\000"
-/* offset=127604 */
-"uncore_sys_ddr_pmu\000"
-/* offset=127623 */
-"sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8\00000\000\000\000\000\000"
-/* offset=127699 */
+/* offset=127726 */
+"uncore_imc_free_running\000"
+/* offset=127750 */
+"uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12\000\00000\000\000\000\000\000"
+/* offset=127830 */
"uncore_sys_ccn_pmu\000"
-/* offset=127718 */
-"sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x01\00000\000\000\000\000\000"
-/* offset=127795 */
+/* offset=127849 */
"uncore_sys_cmn_pmu\000"
-/* offset=127814 */
-"sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first lookup result (high priority)\000eventid=1,type=5\000(434|436|43c|43a).*\00000\000\000\000\000\000"
+/* offset=127868 */
+"uncore_sys_ddr_pmu\000"
+/* offset=127887 */
+"user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000\000\000\000\000\000"
/* offset=127957 */
-"CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPUs\000\000\000\000011"
-/* offset=128143 */
-"cs_per_second\000Default\000software@context\\-switches\\,name\\=context\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\000011"
-/* offset=128376 */
-"migrations_per_second\000Default\000software@cpu\\-migrations\\,name\\=cpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001migrations/sec\000\000\000\000011"
-/* offset=128636 */
-"page_faults_per_second\000Default\000software@page\\-faults\\,name\\=page\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\000011"
-/* offset=128867 */
-"insn_per_cycle\000Default\000instructions / cpu\\-cycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\000\000001"
-/* offset=128980 */
-"stalled_cycles_per_instruction\000Default\000(max(stalled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions if has_event(stalled\\-cycles\\-frontend) & has_event(stalled\\-cycles\\-backend) else (stalled\\-cycles\\-frontend / instructions if has_event(stalled\\-cycles\\-frontend) else (stalled\\-cycles\\-backend / instructions if has_event(stalled\\-cycles\\-backend) else 0)))\000\000Max front or backend stalls per instruction\000\000\000\000\000\000001"
-/* offset=129405 */
-"frontend_cycles_idle\000Default\000(stalled\\-cycles\\-frontend / cpu\\-cycles if has_event(stalled\\-cycles\\-frontend) else 0)\000frontend_cycles_idle > 0.1\000Frontend stalls per cycle\000\000\000\000\000\000001"
-/* offset=129584 */
-"backend_cycles_idle\000Default\000(stalled\\-cycles\\-backend / cpu\\-cycles if has_event(stalled\\-cycles\\-backend) else 0)\000backend_cycles_idle > 0.2\000Backend stalls per cycle\000\000\000\000\000\000001"
-/* offset=129758 */
-"cycles_frequency\000Default\000cpu\\-cycles / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\000\000011"
-/* offset=129934 */
-"branch_frequency\000Default\000branches / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\000\000\000011"
-/* offset=130114 */
-"branch_miss_rate\000Default\000branch\\-misses / branches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\000001"
-/* offset=130218 */
-"l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\000100%\000\000\000\000001"
-/* offset=130334 */
-"llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-loads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\000\000001"
-/* offset=130435 */
-"l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\000100%\000\000\000\000001"
-/* offset=130550 */
-"dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\-loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\000\000\000001"
-/* offset=130656 */
-"itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\-loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\000\000\000001"
-/* offset=130762 */
-"l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch\\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.05\000L1 prefetch miss rate\000\000100%\000\000\000\000001"
-/* offset=130910 */
"CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000"
-/* offset=130933 */
-"IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\000000"
-/* offset=130997 */
-"Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000"
-/* offset=131164 */
-"dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\000000"
-/* offset=131229 */
-"icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\000000"
-/* offset=131297 */
-"cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\000000"
-/* offset=131369 */
+/* offset=127980 */
+"CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@) / (duration_time * 1e9)\000\000Average CPU utilization\000\0001CPUs\000\000\000\000011"
+/* offset=128166 */
+"DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\000000"
+/* offset=128231 */
"DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqsts.rfo_hit\000\000\000\000\000\000\000\000000"
-/* offset=131464 */
+/* offset=128326 */
"DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data_rd_hit, 0) + l2_rqsts.pf_miss + l2_rqsts.rfo_miss\000\000\000\000\000\000\000\000000"
-/* offset=131599 */
-"DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000\000\000\000000"
-/* offset=131664 */
+/* offset=128461 */
"DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000\000\000\000\000000"
-/* offset=131733 */
+/* offset=128530 */
"DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\000\000\000\000\000000"
-/* offset=131804 */
+/* offset=128601 */
+"Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.thread / 2 * (1 + cpu_clk_unhalted.one_thread_active / cpu_clk_unhalted.ref_xclk)))\000\000\000\000\000\000\000\000000"
+/* offset=128768 */
+"IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\000\000\000000"
+/* offset=128832 */
+"L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\000000"
+/* offset=128904 */
"M1\000\000ipc + M2\000\000\000\000\000\000\000\000000"
-/* offset=131827 */
+/* offset=128927 */
"M2\000\000ipc + M1\000\000\000\000\000\000\000\000000"
-/* offset=131850 */
+/* offset=128950 */
"M3\000\0001 / M3\000\000\000\000\000\000\000\000000"
-/* offset=131871 */
-"L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\000\000\000\000\000000"
+/* offset=128971 */
+"backend_cycles_idle\000Default\000(stalled\\-cycles\\-backend / cpu\\-cycles if has_event(stalled\\-cycles\\-backend) else 0)\000backend_cycles_idle > 0.2\000Backend stalls per cycle\000\000\000\000\000\000001"
+/* offset=129145 */
+"branch_frequency\000Default\000branches / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Branches per CPU second\000\0001000M/sec\000\000\000\000011"
+/* offset=129325 */
+"branch_miss_rate\000Default\000branch\\-misses / branches\000branch_miss_rate > 0.05\000Branch miss rate\000\000100%\000\000\000\000001"
+/* offset=129429 */
+"cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\000\000\000\000\000000"
+/* offset=129501 */
+"cs_per_second\000Default\000software@context\\-switches\\,name\\=context\\-switches@ * 1e9 / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Context switches per CPU second\000\0001cs/sec\000\000\000\000011"
+/* offset=129734 */
+"cycles_frequency\000Default\000cpu\\-cycles / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Cycles per CPU second\000\0001GHz\000\000\000\000011"
+/* offset=129910 */
+"dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\000000"
+/* offset=129975 */
+"dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\-loads\000dtlb_miss_rate > 0.05\000dTLB miss rate\000\000100%\000\000\000\000001"
+/* offset=130081 */
+"frontend_cycles_idle\000Default\000(stalled\\-cycles\\-frontend / cpu\\-cycles if has_event(stalled\\-cycles\\-frontend) else 0)\000frontend_cycles_idle > 0.1\000Frontend stalls per cycle\000\000\000\000\000\000001"
+/* offset=130260 */
+"icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\000\000\000\000\000000"
+/* offset=130328 */
+"insn_per_cycle\000Default\000instructions / cpu\\-cycles\000insn_per_cycle < 1\000Instructions Per Cycle\000\0001instructions\000\000\000\000001"
+/* offset=130441 */
+"itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\-loads\000itlb_miss_rate > 0.05\000iTLB miss rate\000\000100%\000\000\000\000001"
+/* offset=130547 */
+"l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch\\-misses / L1\\-dcache\\-prefetches\000l1_prefetch_miss_rate > 0.05\000L1 prefetch miss rate\000\000100%\000\000\000\000001"
+/* offset=130695 */
+"l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / L1\\-dcache\\-loads\000l1d_miss_rate > 0.05\000L1D miss rate\000\000100%\000\000\000\000001"
+/* offset=130811 */
+"l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / L1\\-icache\\-loads\000l1i_miss_rate > 0.05\000L1I miss rate\000\000100%\000\000\000\000001"
+/* offset=130926 */
+"llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-loads\000llc_miss_rate > 0.05\000LLC miss rate\000\000100%\000\000\000\000001"
+/* offset=131027 */
+"migrations_per_second\000Default\000software@cpu\\-migrations\\,name\\=cpu\\-migrations@ * 1e9 / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Process migrations to a new CPU per CPU second\000\0001migrations/sec\000\000\000\000011"
+/* offset=131287 */
+"page_faults_per_second\000Default\000software@page\\-faults\\,name\\=page\\-faults@ * 1e9 / (software@cpu\\-clock\\,name\\=cpu\\-clock@ if #target_cpu else software@task\\-clock\\,name\\=task\\-clock@)\000\000Page faults per CPU second\000\0001faults/sec\000\000\000\000011"
+/* offset=131518 */
+"stalled_cycles_per_instruction\000Default\000(max(stalled\\-cycles\\-frontend, stalled\\-cycles\\-backend) / instructions if has_event(stalled\\-cycles\\-frontend) & has_event(stalled\\-cycles\\-backend) else (stalled\\-cycles\\-frontend / instructions if has_event(stalled\\-cycles\\-frontend) else (stalled\\-cycles\\-backend / instructions if has_event(stalled\\-cycles\\-backend) else 0)))\000\000Max front or backend stalls per instruction\000\000\000\000\000\000001"
;
static const struct compact_pmu_event pmu_events__common_default_core[] = {
/* bpc\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-conf... */
- { 111480 },
+ { 216 },
/* bpc-access\000legacy cache\000Branch prediction unit read accesses\000legacy-cac... */
- { 113849 },
+ { 300 },
/* bpc-load\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 111564 },
+ { 391 },
/* bpc-load-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 111939 },
+ { 480 },
/* bpc-load-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 112135 },
+ { 576 },
/* bpc-load-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 112035 },
+ { 674 },
/* bpc-load-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 111846 },
+ { 774 },
/* bpc-load-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 111747 },
+ { 867 },
/* bpc-load-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 111653 },
+ { 966 },
/* bpc-loads\000legacy cache\000Branch prediction unit read accesses\000legacy-cach... */
- { 112233 },
+ { 1060 },
/* bpc-loads-access\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 112612 },
+ { 1150 },
/* bpc-loads-miss\000legacy cache\000Branch prediction unit read misses\000legacy-c... */
- { 112810 },
+ { 1247 },
/* bpc-loads-misses\000legacy cache\000Branch prediction unit read misses\000legacy... */
- { 112709 },
+ { 1346 },
/* bpc-loads-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 112518 },
+ { 1447 },
/* bpc-loads-reference\000legacy cache\000Branch prediction unit read accesses\000l... */
- { 112418 },
+ { 1541 },
/* bpc-loads-refs\000legacy cache\000Branch prediction unit read accesses\000legacy... */
- { 112323 },
+ { 1641 },
/* bpc-miss\000legacy cache\000Branch prediction unit read misses\000legacy-cache-c... */
- { 114035 },
+ { 1736 },
/* bpc-misses\000legacy cache\000Branch prediction unit read misses\000legacy-cache... */
- { 113940 },
+ { 1829 },
/* bpc-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-... */
- { 113761 },
+ { 1924 },
/* bpc-read\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 112909 },
+ { 2012 },
/* bpc-read-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 113284 },
+ { 2101 },
/* bpc-read-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 113480 },
+ { 2197 },
/* bpc-read-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 113380 },
+ { 2295 },
/* bpc-read-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 113191 },
+ { 2395 },
/* bpc-read-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 113092 },
+ { 2488 },
/* bpc-read-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 112998 },
+ { 2587 },
/* bpc-reference\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 113667 },
+ { 2681 },
/* bpc-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 113578 },
+ { 2775 },
/* bpu\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-conf... */
- { 106184 },
+ { 2966 },
/* bpu-access\000legacy cache\000Branch prediction unit read accesses\000legacy-cac... */
- { 108553 },
+ { 3050 },
/* bpu-load\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 106268 },
+ { 3141 },
/* bpu-load-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 106643 },
+ { 3230 },
/* bpu-load-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 106839 },
+ { 3326 },
/* bpu-load-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 106739 },
+ { 3424 },
/* bpu-load-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 106550 },
+ { 3524 },
/* bpu-load-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 106451 },
+ { 3617 },
/* bpu-load-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 106357 },
+ { 3716 },
/* bpu-loads\000legacy cache\000Branch prediction unit read accesses\000legacy-cach... */
- { 106937 },
+ { 3810 },
/* bpu-loads-access\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 107316 },
+ { 3900 },
/* bpu-loads-miss\000legacy cache\000Branch prediction unit read misses\000legacy-c... */
- { 107514 },
+ { 3997 },
/* bpu-loads-misses\000legacy cache\000Branch prediction unit read misses\000legacy... */
- { 107413 },
+ { 4096 },
/* bpu-loads-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 107222 },
+ { 4197 },
/* bpu-loads-reference\000legacy cache\000Branch prediction unit read accesses\000l... */
- { 107122 },
+ { 4291 },
/* bpu-loads-refs\000legacy cache\000Branch prediction unit read accesses\000legacy... */
- { 107027 },
+ { 4391 },
/* bpu-miss\000legacy cache\000Branch prediction unit read misses\000legacy-cache-c... */
- { 108739 },
+ { 4486 },
/* bpu-misses\000legacy cache\000Branch prediction unit read misses\000legacy-cache... */
- { 108644 },
+ { 4579 },
/* bpu-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-... */
- { 108465 },
+ { 4674 },
/* bpu-read\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 107613 },
+ { 4762 },
/* bpu-read-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 107988 },
+ { 4851 },
/* bpu-read-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 108184 },
+ { 4947 },
/* bpu-read-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 108084 },
+ { 5045 },
/* bpu-read-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 107895 },
+ { 5145 },
/* bpu-read-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 107796 },
+ { 5238 },
/* bpu-read-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 107702 },
+ { 5337 },
/* bpu-reference\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 108371 },
+ { 5431 },
/* bpu-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 108282 },
+ { 5525 },
/* branch\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-c... */
- { 100851 },
+ { 5614 },
/* branch-access\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 103295 },
+ { 5701 },
/* branch-instructions\000legacy hardware\000Retired branch instructions [This even... */
- { 122452 },
+ { 5795 },
/* branch-load\000legacy cache\000Branch prediction unit read accesses\000legacy-ca... */
- { 100938 },
+ { 5929 },
/* branch-load-access\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 101325 },
+ { 6021 },
/* branch-load-miss\000legacy cache\000Branch prediction unit read misses\000legacy... */
- { 101527 },
+ { 6120 },
/* branch-load-misses\000legacy cache\000Branch prediction unit read misses\000lega... */
- { 101424 },
+ { 6221 },
/* branch-load-ops\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 101229 },
+ { 6324 },
/* branch-load-reference\000legacy cache\000Branch prediction unit read accesses\00... */
- { 101127 },
+ { 6420 },
/* branch-load-refs\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 101030 },
+ { 6522 },
/* branch-loads\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 101628 },
+ { 6619 },
/* branch-loads-access\000legacy cache\000Branch prediction unit read accesses\000l... */
- { 102019 },
+ { 6712 },
/* branch-loads-miss\000legacy cache\000Branch prediction unit read misses\000legac... */
- { 102223 },
+ { 6812 },
/* branch-loads-misses\000legacy cache\000Branch prediction unit read misses\000leg... */
- { 102119 },
+ { 6914 },
/* branch-loads-ops\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 101922 },
+ { 7018 },
/* branch-loads-reference\000legacy cache\000Branch prediction unit read accesses\0... */
- { 101819 },
+ { 7115 },
/* branch-loads-refs\000legacy cache\000Branch prediction unit read accesses\000leg... */
- { 101721 },
+ { 7218 },
/* branch-miss\000legacy cache\000Branch prediction unit read misses\000legacy-cach... */
- { 103389 },
+ { 7316 },
/* branch-misses\000legacy hardware\000Mispredicted branch instructions\000legacy-h... */
- { 122586 },
+ { 7412 },
/* branch-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-cac... */
- { 103204 },
+ { 7508 },
/* branch-read\000legacy cache\000Branch prediction unit read accesses\000legacy-ca... */
- { 102325 },
+ { 7599 },
/* branch-read-access\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 102712 },
+ { 7691 },
/* branch-read-miss\000legacy cache\000Branch prediction unit read misses\000legacy... */
- { 102914 },
+ { 7790 },
/* branch-read-misses\000legacy cache\000Branch prediction unit read misses\000lega... */
- { 102811 },
+ { 7891 },
/* branch-read-ops\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 102616 },
+ { 7994 },
/* branch-read-reference\000legacy cache\000Branch prediction unit read accesses\00... */
- { 102514 },
+ { 8090 },
/* branch-read-refs\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 102417 },
+ { 8192 },
/* branch-reference\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 103107 },
+ { 8289 },
/* branch-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-ca... */
- { 103015 },
+ { 8386 },
/* branches\000legacy hardware\000Retired branch instructions [This event is an ali... */
- { 122318 },
+ { 8478 },
/* branches-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 105890 },
+ { 8612 },
/* branches-load\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 103485 },
+ { 8708 },
/* branches-load-access\000legacy cache\000Branch prediction unit read accesses\000... */
- { 103880 },
+ { 8802 },
/* branches-load-miss\000legacy cache\000Branch prediction unit read misses\000lega... */
- { 104086 },
+ { 8903 },
/* branches-load-misses\000legacy cache\000Branch prediction unit read misses\000le... */
- { 103981 },
+ { 9006 },
/* branches-load-ops\000legacy cache\000Branch prediction unit read accesses\000leg... */
- { 103782 },
+ { 9111 },
/* branches-load-reference\000legacy cache\000Branch prediction unit read accesses\... */
- { 103678 },
+ { 9209 },
/* branches-load-refs\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 103579 },
+ { 9313 },
/* branches-loads\000legacy cache\000Branch prediction unit read accesses\000legacy... */
- { 104189 },
+ { 9412 },
/* branches-loads-access\000legacy cache\000Branch prediction unit read accesses\00... */
- { 104588 },
+ { 9507 },
/* branches-loads-miss\000legacy cache\000Branch prediction unit read misses\000leg... */
- { 104796 },
+ { 9609 },
/* branches-loads-misses\000legacy cache\000Branch prediction unit read misses\000l... */
- { 104690 },
+ { 9713 },
/* branches-loads-ops\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 104489 },
+ { 9819 },
/* branches-loads-reference\000legacy cache\000Branch prediction unit read accesses... */
- { 104384 },
+ { 9918 },
/* branches-loads-refs\000legacy cache\000Branch prediction unit read accesses\000l... */
- { 104284 },
+ { 10023 },
/* branches-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 106086 },
+ { 10123 },
/* branches-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 105986 },
+ { 10221 },
/* branches-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 105797 },
+ { 10321 },
/* branches-read\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 104900 },
+ { 10414 },
/* branches-read-access\000legacy cache\000Branch prediction unit read accesses\000... */
- { 105295 },
+ { 10508 },
/* branches-read-miss\000legacy cache\000Branch prediction unit read misses\000lega... */
- { 105501 },
+ { 10609 },
/* branches-read-misses\000legacy cache\000Branch prediction unit read misses\000le... */
- { 105396 },
+ { 10712 },
/* branches-read-ops\000legacy cache\000Branch prediction unit read accesses\000leg... */
- { 105197 },
+ { 10817 },
/* branches-read-reference\000legacy cache\000Branch prediction unit read accesses\... */
- { 105093 },
+ { 10915 },
/* branches-read-refs\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 104994 },
+ { 11019 },
/* branches-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 105698 },
+ { 11118 },
/* branches-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 105604 },
+ { 11217 },
/* btb\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-conf... */
- { 108832 },
+ { 11311 },
/* btb-access\000legacy cache\000Branch prediction unit read accesses\000legacy-cac... */
- { 111201 },
+ { 11395 },
/* btb-load\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 108916 },
+ { 11486 },
/* btb-load-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 109291 },
+ { 11575 },
/* btb-load-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 109487 },
+ { 11671 },
/* btb-load-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 109387 },
+ { 11769 },
/* btb-load-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 109198 },
+ { 11869 },
/* btb-load-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 109099 },
+ { 11962 },
/* btb-load-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 109005 },
+ { 12061 },
/* btb-loads\000legacy cache\000Branch prediction unit read accesses\000legacy-cach... */
- { 109585 },
+ { 12155 },
/* btb-loads-access\000legacy cache\000Branch prediction unit read accesses\000lega... */
- { 109964 },
+ { 12245 },
/* btb-loads-miss\000legacy cache\000Branch prediction unit read misses\000legacy-c... */
- { 110162 },
+ { 12342 },
/* btb-loads-misses\000legacy cache\000Branch prediction unit read misses\000legacy... */
- { 110061 },
+ { 12441 },
/* btb-loads-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 109870 },
+ { 12542 },
/* btb-loads-reference\000legacy cache\000Branch prediction unit read accesses\000l... */
- { 109770 },
+ { 12636 },
/* btb-loads-refs\000legacy cache\000Branch prediction unit read accesses\000legacy... */
- { 109675 },
+ { 12736 },
/* btb-miss\000legacy cache\000Branch prediction unit read misses\000legacy-cache-c... */
- { 111387 },
+ { 12831 },
/* btb-misses\000legacy cache\000Branch prediction unit read misses\000legacy-cache... */
- { 111292 },
+ { 12924 },
/* btb-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-cache-... */
- { 111113 },
+ { 13019 },
/* btb-read\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 110261 },
+ { 13107 },
/* btb-read-access\000legacy cache\000Branch prediction unit read accesses\000legac... */
- { 110636 },
+ { 13196 },
/* btb-read-miss\000legacy cache\000Branch prediction unit read misses\000legacy-ca... */
- { 110832 },
+ { 13292 },
/* btb-read-misses\000legacy cache\000Branch prediction unit read misses\000legacy-... */
- { 110732 },
+ { 13390 },
/* btb-read-ops\000legacy cache\000Branch prediction unit read accesses\000legacy-c... */
- { 110543 },
+ { 13490 },
/* btb-read-reference\000legacy cache\000Branch prediction unit read accesses\000le... */
- { 110444 },
+ { 13583 },
/* btb-read-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 110350 },
+ { 13682 },
/* btb-reference\000legacy cache\000Branch prediction unit read accesses\000legacy-... */
- { 111019 },
+ { 13776 },
/* btb-refs\000legacy cache\000Branch prediction unit read accesses\000legacy-cache... */
- { 110930 },
+ { 13870 },
/* bus-cycles\000legacy hardware\000Bus cycles, which can be different from total c... */
- { 122682 },
+ { 13959 },
/* cache-misses\000legacy hardware\000Cache misses. Usually this indicates Last Lev... */
- { 122075 },
+ { 14072 },
/* cache-references\000legacy hardware\000Cache accesses. Usually this indicates La... */
- { 121805 },
+ { 14315 },
/* cpu-cycles\000legacy hardware\000Total cycles. Be wary of what happens during CP... */
- { 121305 },
+ { 14989 },
/* cycles\000legacy hardware\000Total cycles. Be wary of what happens during CPU fr... */
- { 121467 },
+ { 15384 },
/* d-tlb\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\000... */
- { 78952 },
+ { 15546 },
/* d-tlb-access\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\... */
- { 85655 },
+ { 15618 },
/* d-tlb-load\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\00... */
- { 79024 },
+ { 15697 },
/* d-tlb-load-access\000legacy cache\000Data TLB read accesses\000legacy-cache-conf... */
- { 79351 },
+ { 15774 },
/* d-tlb-load-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0... */
- { 79523 },
+ { 15858 },
/* d-tlb-load-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config... */
- { 79435 },
+ { 15944 },
/* d-tlb-load-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=... */
- { 79270 },
+ { 16032 },
/* d-tlb-load-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-c... */
- { 79183 },
+ { 16113 },
/* d-tlb-load-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-config... */
- { 79101 },
+ { 16200 },
/* d-tlb-loads\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\0... */
- { 79609 },
+ { 16282 },
/* d-tlb-loads-access\000legacy cache\000Data TLB read accesses\000legacy-cache-con... */
- { 79940 },
+ { 16360 },
/* d-tlb-loads-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=... */
- { 80114 },
+ { 16445 },
/* d-tlb-loads-misses\000legacy cache\000Data TLB read misses\000legacy-cache-confi... */
- { 80025 },
+ { 16532 },
/* d-tlb-loads-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config... */
- { 79858 },
+ { 16621 },
/* d-tlb-loads-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-... */
- { 79770 },
+ { 16703 },
/* d-tlb-loads-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-confi... */
- { 79687 },
+ { 16791 },
/* d-tlb-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x1000... */
- { 85817 },
+ { 16874 },
/* d-tlb-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x10... */
- { 85734 },
+ { 16955 },
/* d-tlb-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000... */
- { 85579 },
+ { 17038 },
/* d-tlb-prefetch\000legacy cache\000Data TLB prefetch accesses\000legacy-cache-con... */
- { 82650 },
+ { 17114 },
/* d-tlb-prefetch-access\000legacy cache\000Data TLB prefetch accesses\000legacy-ca... */
- { 83025 },
+ { 17203 },
/* d-tlb-prefetch-miss\000legacy cache\000Data TLB prefetch misses\000legacy-cache-... */
- { 83217 },
+ { 17299 },
/* d-tlb-prefetch-misses\000legacy cache\000Data TLB prefetch misses\000legacy-cach... */
- { 83121 },
+ { 17393 },
/* d-tlb-prefetch-ops\000legacy cache\000Data TLB prefetch accesses\000legacy-cache... */
- { 82932 },
+ { 17489 },
/* d-tlb-prefetch-reference\000legacy cache\000Data TLB prefetch accesses\000legacy... */
- { 82833 },
+ { 17582 },
/* d-tlb-prefetch-refs\000legacy cache\000Data TLB prefetch accesses\000legacy-cach... */
- { 82739 },
+ { 17681 },
/* d-tlb-prefetches\000legacy cache\000Data TLB prefetch accesses\000legacy-cache-c... */
- { 83311 },
+ { 17775 },
/* d-tlb-prefetches-access\000legacy cache\000Data TLB prefetch accesses\000legacy-... */
- { 83694 },
+ { 17866 },
/* d-tlb-prefetches-miss\000legacy cache\000Data TLB prefetch misses\000legacy-cach... */
- { 83890 },
+ { 17964 },
/* d-tlb-prefetches-misses\000legacy cache\000Data TLB prefetch misses\000legacy-ca... */
- { 83792 },
+ { 18060 },
/* d-tlb-prefetches-ops\000legacy cache\000Data TLB prefetch accesses\000legacy-cac... */
- { 83599 },
+ { 18158 },
/* d-tlb-prefetches-reference\000legacy cache\000Data TLB prefetch accesses\000lega... */
- { 83498 },
+ { 18253 },
/* d-tlb-prefetches-refs\000legacy cache\000Data TLB prefetch accesses\000legacy-ca... */
- { 83402 },
+ { 18354 },
/* d-tlb-read\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\00... */
- { 80201 },
+ { 18450 },
/* d-tlb-read-access\000legacy cache\000Data TLB read accesses\000legacy-cache-conf... */
- { 80528 },
+ { 18527 },
/* d-tlb-read-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0... */
- { 80700 },
+ { 18611 },
/* d-tlb-read-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config... */
- { 80612 },
+ { 18697 },
/* d-tlb-read-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=... */
- { 80447 },
+ { 18785 },
/* d-tlb-read-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-c... */
- { 80360 },
+ { 18866 },
/* d-tlb-read-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-config... */
- { 80278 },
+ { 18953 },
/* d-tlb-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-config... */
- { 85497 },
+ { 19035 },
/* d-tlb-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\00... */
- { 85420 },
+ { 19117 },
/* d-tlb-speculative-load\000legacy cache\000Data TLB prefetch accesses\000legacy-c... */
- { 84703 },
+ { 19194 },
/* d-tlb-speculative-load-access\000legacy cache\000Data TLB prefetch accesses\000l... */
- { 85110 },
+ { 19291 },
/* d-tlb-speculative-load-miss\000legacy cache\000Data TLB prefetch misses\000legac... */
- { 85318 },
+ { 19395 },
/* d-tlb-speculative-load-misses\000legacy cache\000Data TLB prefetch misses\000leg... */
- { 85214 },
+ { 19497 },
/* d-tlb-speculative-load-ops\000legacy cache\000Data TLB prefetch accesses\000lega... */
- { 85009 },
+ { 19601 },
/* d-tlb-speculative-load-reference\000legacy cache\000Data TLB prefetch accesses\0... */
- { 84902 },
+ { 19702 },
/* d-tlb-speculative-load-refs\000legacy cache\000Data TLB prefetch accesses\000leg... */
- { 84800 },
+ { 19809 },
/* d-tlb-speculative-read\000legacy cache\000Data TLB prefetch accesses\000legacy-c... */
- { 83986 },
+ { 19911 },
/* d-tlb-speculative-read-access\000legacy cache\000Data TLB prefetch accesses\000l... */
- { 84393 },
+ { 20008 },
/* d-tlb-speculative-read-miss\000legacy cache\000Data TLB prefetch misses\000legac... */
- { 84601 },
+ { 20112 },
/* d-tlb-speculative-read-misses\000legacy cache\000Data TLB prefetch misses\000leg... */
- { 84497 },
+ { 20214 },
/* d-tlb-speculative-read-ops\000legacy cache\000Data TLB prefetch accesses\000lega... */
- { 84292 },
+ { 20318 },
/* d-tlb-speculative-read-reference\000legacy cache\000Data TLB prefetch accesses\0... */
- { 84185 },
+ { 20419 },
/* d-tlb-speculative-read-refs\000legacy cache\000Data TLB prefetch accesses\000leg... */
- { 84083 },
+ { 20526 },
/* d-tlb-store\000legacy cache\000Data TLB write accesses\000legacy-cache-config=0x... */
- { 80786 },
+ { 20628 },
/* d-tlb-store-access\000legacy cache\000Data TLB write accesses\000legacy-cache-co... */
- { 81137 },
+ { 20711 },
/* d-tlb-store-miss\000legacy cache\000Data TLB write misses\000legacy-cache-config... */
- { 81317 },
+ { 20801 },
/* d-tlb-store-misses\000legacy cache\000Data TLB write misses\000legacy-cache-conf... */
- { 81227 },
+ { 20889 },
/* d-tlb-store-ops\000legacy cache\000Data TLB write accesses\000legacy-cache-confi... */
- { 81050 },
+ { 20979 },
/* d-tlb-store-reference\000legacy cache\000Data TLB write accesses\000legacy-cache... */
- { 80957 },
+ { 21066 },
/* d-tlb-store-refs\000legacy cache\000Data TLB write accesses\000legacy-cache-conf... */
- { 80869 },
+ { 21159 },
/* d-tlb-stores\000legacy cache\000Data TLB write accesses\000legacy-cache-config=0... */
- { 81405 },
+ { 21247 },
/* d-tlb-stores-access\000legacy cache\000Data TLB write accesses\000legacy-cache-c... */
- { 81760 },
+ { 21331 },
/* d-tlb-stores-miss\000legacy cache\000Data TLB write misses\000legacy-cache-confi... */
- { 81942 },
+ { 21422 },
/* d-tlb-stores-misses\000legacy cache\000Data TLB write misses\000legacy-cache-con... */
- { 81851 },
+ { 21511 },
/* d-tlb-stores-ops\000legacy cache\000Data TLB write accesses\000legacy-cache-conf... */
- { 81672 },
+ { 21602 },
/* d-tlb-stores-reference\000legacy cache\000Data TLB write accesses\000legacy-cach... */
- { 81578 },
+ { 21690 },
/* d-tlb-stores-refs\000legacy cache\000Data TLB write accesses\000legacy-cache-con... */
- { 81489 },
+ { 21784 },
/* d-tlb-write\000legacy cache\000Data TLB write accesses\000legacy-cache-config=0x... */
- { 82031 },
+ { 21873 },
/* d-tlb-write-access\000legacy cache\000Data TLB write accesses\000legacy-cache-co... */
- { 82382 },
+ { 21956 },
/* d-tlb-write-miss\000legacy cache\000Data TLB write misses\000legacy-cache-config... */
- { 82562 },
+ { 22046 },
/* d-tlb-write-misses\000legacy cache\000Data TLB write misses\000legacy-cache-conf... */
- { 82472 },
+ { 22134 },
/* d-tlb-write-ops\000legacy cache\000Data TLB write accesses\000legacy-cache-confi... */
- { 82295 },
+ { 22224 },
/* d-tlb-write-reference\000legacy cache\000Data TLB write accesses\000legacy-cache... */
- { 82202 },
+ { 22311 },
/* d-tlb-write-refs\000legacy cache\000Data TLB write accesses\000legacy-cache-conf... */
- { 82114 },
+ { 22404 },
/* data-tlb\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\... */
- { 85898 },
+ { 22492 },
/* data-tlb-access\000legacy cache\000Data TLB read accesses\000legacy-cache-config... */
- { 92823 },
+ { 22567 },
/* data-tlb-load\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3... */
- { 85973 },
+ { 22649 },
/* data-tlb-load-access\000legacy cache\000Data TLB read accesses\000legacy-cache-c... */
- { 86312 },
+ { 22729 },
/* data-tlb-load-miss\000legacy cache\000Data TLB read misses\000legacy-cache-confi... */
- { 86490 },
+ { 22816 },
/* data-tlb-load-misses\000legacy cache\000Data TLB read misses\000legacy-cache-con... */
- { 86399 },
+ { 22905 },
/* data-tlb-load-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-conf... */
- { 86228 },
+ { 22996 },
/* data-tlb-load-reference\000legacy cache\000Data TLB read accesses\000legacy-cach... */
- { 86138 },
+ { 23080 },
/* data-tlb-load-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-con... */
- { 86053 },
+ { 23170 },
/* data-tlb-loads\000legacy cache\000Data TLB read accesses\000legacy-cache-config=... */
- { 86579 },
+ { 23255 },
/* data-tlb-loads-access\000legacy cache\000Data TLB read accesses\000legacy-cache-... */
- { 86922 },
+ { 23336 },
/* data-tlb-loads-miss\000legacy cache\000Data TLB read misses\000legacy-cache-conf... */
- { 87102 },
+ { 23424 },
/* data-tlb-loads-misses\000legacy cache\000Data TLB read misses\000legacy-cache-co... */
- { 87010 },
+ { 23514 },
/* data-tlb-loads-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-con... */
- { 86837 },
+ { 23606 },
/* data-tlb-loads-reference\000legacy cache\000Data TLB read accesses\000legacy-cac... */
- { 86746 },
+ { 23691 },
/* data-tlb-loads-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-co... */
- { 86660 },
+ { 23782 },
/* data-tlb-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x1... */
- { 92991 },
+ { 23868 },
/* data-tlb-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config=0... */
- { 92905 },
+ { 23952 },
/* data-tlb-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\... */
- { 92744 },
+ { 24038 },
/* data-tlb-prefetch\000legacy cache\000Data TLB prefetch accesses\000legacy-cache-... */
- { 89725 },
+ { 24117 },
/* data-tlb-prefetch-access\000legacy cache\000Data TLB prefetch accesses\000legacy... */
- { 90112 },
+ { 24209 },
/* data-tlb-prefetch-miss\000legacy cache\000Data TLB prefetch misses\000legacy-cac... */
- { 90310 },
+ { 24308 },
/* data-tlb-prefetch-misses\000legacy cache\000Data TLB prefetch misses\000legacy-c... */
- { 90211 },
+ { 24405 },
/* data-tlb-prefetch-ops\000legacy cache\000Data TLB prefetch accesses\000legacy-ca... */
- { 90016 },
+ { 24504 },
/* data-tlb-prefetch-reference\000legacy cache\000Data TLB prefetch accesses\000leg... */
- { 89914 },
+ { 24600 },
/* data-tlb-prefetch-refs\000legacy cache\000Data TLB prefetch accesses\000legacy-c... */
- { 89817 },
+ { 24702 },
/* data-tlb-prefetches\000legacy cache\000Data TLB prefetch accesses\000legacy-cach... */
- { 90407 },
+ { 24799 },
/* data-tlb-prefetches-access\000legacy cache\000Data TLB prefetch accesses\000lega... */
- { 90802 },
+ { 24893 },
/* data-tlb-prefetches-miss\000legacy cache\000Data TLB prefetch misses\000legacy-c... */
- { 91004 },
+ { 24994 },
/* data-tlb-prefetches-misses\000legacy cache\000Data TLB prefetch misses\000legacy... */
- { 90903 },
+ { 25093 },
/* data-tlb-prefetches-ops\000legacy cache\000Data TLB prefetch accesses\000legacy-... */
- { 90704 },
+ { 25194 },
/* data-tlb-prefetches-reference\000legacy cache\000Data TLB prefetch accesses\000l... */
- { 90600 },
+ { 25292 },
/* data-tlb-prefetches-refs\000legacy cache\000Data TLB prefetch accesses\000legacy... */
- { 90501 },
+ { 25396 },
/* data-tlb-read\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3... */
- { 87192 },
+ { 25495 },
/* data-tlb-read-access\000legacy cache\000Data TLB read accesses\000legacy-cache-c... */
- { 87531 },
+ { 25575 },
/* data-tlb-read-miss\000legacy cache\000Data TLB read misses\000legacy-cache-confi... */
- { 87709 },
+ { 25662 },
/* data-tlb-read-misses\000legacy cache\000Data TLB read misses\000legacy-cache-con... */
- { 87618 },
+ { 25751 },
/* data-tlb-read-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-conf... */
- { 87447 },
+ { 25842 },
/* data-tlb-read-reference\000legacy cache\000Data TLB read accesses\000legacy-cach... */
- { 87357 },
+ { 25926 },
/* data-tlb-read-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-con... */
- { 87272 },
+ { 26016 },
/* data-tlb-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-con... */
- { 92659 },
+ { 26101 },
/* data-tlb-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3... */
- { 92579 },
+ { 26186 },
/* data-tlb-speculative-load\000legacy cache\000Data TLB prefetch accesses\000legac... */
- { 91841 },
+ { 26266 },
/* data-tlb-speculative-load-access\000legacy cache\000Data TLB prefetch accesses\0... */
- { 92260 },
+ { 26366 },
/* data-tlb-speculative-load-miss\000legacy cache\000Data TLB prefetch misses\000le... */
- { 92474 },
+ { 26473 },
/* data-tlb-speculative-load-misses\000legacy cache\000Data TLB prefetch misses\000... */
- { 92367 },
+ { 26578 },
/* data-tlb-speculative-load-ops\000legacy cache\000Data TLB prefetch accesses\000l... */
- { 92156 },
+ { 26685 },
/* data-tlb-speculative-load-reference\000legacy cache\000Data TLB prefetch accesse... */
- { 92046 },
+ { 26789 },
/* data-tlb-speculative-load-refs\000legacy cache\000Data TLB prefetch accesses\000... */
- { 91941 },
+ { 26899 },
/* data-tlb-speculative-read\000legacy cache\000Data TLB prefetch accesses\000legac... */
- { 91103 },
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/* data-tlb-store\000legacy cache\000Data TLB write accesses\000legacy-cache-config... */
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/* data-tlb-store-access\000legacy cache\000Data TLB write accesses\000legacy-cache... */
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/* data-tlb-store-miss\000legacy cache\000Data TLB write misses\000legacy-cache-con... */
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/* data-tlb-store-misses\000legacy cache\000Data TLB write misses\000legacy-cache-c... */
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/* data-tlb-store-ops\000legacy cache\000Data TLB write accesses\000legacy-cache-co... */
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/* data-tlb-store-reference\000legacy cache\000Data TLB write accesses\000legacy-ca... */
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/* data-tlb-store-refs\000legacy cache\000Data TLB write accesses\000legacy-cache-c... */
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/* data-tlb-stores\000legacy cache\000Data TLB write accesses\000legacy-cache-confi... */
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/* data-tlb-stores-access\000legacy cache\000Data TLB write accesses\000legacy-cach... */
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/* data-tlb-stores-miss\000legacy cache\000Data TLB write misses\000legacy-cache-co... */
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/* data-tlb-stores-misses\000legacy cache\000Data TLB write misses\000legacy-cache-... */
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/* data-tlb-stores-ops\000legacy cache\000Data TLB write accesses\000legacy-cache-c... */
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/* data-tlb-stores-reference\000legacy cache\000Data TLB write accesses\000legacy-c... */
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/* data-tlb-write\000legacy cache\000Data TLB write accesses\000legacy-cache-config... */
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/* data-tlb-write-access\000legacy cache\000Data TLB write accesses\000legacy-cache... */
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/* data-tlb-write-miss\000legacy cache\000Data TLB write misses\000legacy-cache-con... */
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/* data-tlb-write-misses\000legacy cache\000Data TLB write misses\000legacy-cache-c... */
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/* data-tlb-write-ops\000legacy cache\000Data TLB write accesses\000legacy-cache-co... */
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/* data-tlb-write-reference\000legacy cache\000Data TLB write accesses\000legacy-ca... */
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/* data-tlb-write-refs\000legacy cache\000Data TLB write accesses\000legacy-cache-c... */
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/* dtlb\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\0001... */
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/* dtlb-access\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\0... */
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/* dtlb-load\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000... */
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/* dtlb-load-access\000legacy cache\000Data TLB read accesses\000legacy-cache-confi... */
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/* dtlb-load-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x... */
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/* dtlb-load-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config=... */
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/* dtlb-load-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3... */
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/* dtlb-load-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-co... */
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/* dtlb-loads\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\00... */
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/* dtlb-loads-access\000legacy cache\000Data TLB read accesses\000legacy-cache-conf... */
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/* dtlb-loads-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0... */
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/* dtlb-loads-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config... */
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/* dtlb-loads-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=... */
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/* dtlb-loads-reference\000legacy cache\000Data TLB read accesses\000legacy-cache-c... */
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/* dtlb-loads-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-config... */
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/* dtlb-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x10003... */
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/* dtlb-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x100... */
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/* dtlb-ops\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000\... */
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/* dtlb-prefetch\000legacy cache\000Data TLB prefetch accesses\000legacy-cache-conf... */
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/* dtlb-prefetch-access\000legacy cache\000Data TLB prefetch accesses\000legacy-cac... */
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/* dtlb-prefetch-miss\000legacy cache\000Data TLB prefetch misses\000legacy-cache-c... */
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/* dtlb-prefetch-misses\000legacy cache\000Data TLB prefetch misses\000legacy-cache... */
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/* dtlb-prefetch-ops\000legacy cache\000Data TLB prefetch accesses\000legacy-cache-... */
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/* dtlb-prefetch-reference\000legacy cache\000Data TLB prefetch accesses\000legacy-... */
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/* dtlb-prefetch-refs\000legacy cache\000Data TLB prefetch accesses\000legacy-cache... */
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/* dtlb-prefetches\000legacy cache\000Data TLB prefetch accesses\000legacy-cache-co... */
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/* dtlb-prefetches-access\000legacy cache\000Data TLB prefetch accesses\000legacy-c... */
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/* dtlb-prefetches-misses\000legacy cache\000Data TLB prefetch misses\000legacy-cac... */
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/* dtlb-prefetches-ops\000legacy cache\000Data TLB prefetch accesses\000legacy-cach... */
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/* dtlb-prefetches-reference\000legacy cache\000Data TLB prefetch accesses\000legac... */
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/* dtlb-prefetches-refs\000legacy cache\000Data TLB prefetch accesses\000legacy-cac... */
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/* dtlb-read\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000... */
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/* dtlb-read-access\000legacy cache\000Data TLB read accesses\000legacy-cache-confi... */
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/* dtlb-read-miss\000legacy cache\000Data TLB read misses\000legacy-cache-config=0x... */
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/* dtlb-read-misses\000legacy cache\000Data TLB read misses\000legacy-cache-config=... */
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/* dtlb-refs\000legacy cache\000Data TLB read accesses\000legacy-cache-config=3\000... */
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/* dtlb-speculative-read-reference\000legacy cache\000Data TLB prefetch accesses\00... */
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/* dtlb-speculative-read-refs\000legacy cache\000Data TLB prefetch accesses\000lega... */
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/* dtlb-stores-refs\000legacy cache\000Data TLB write accesses\000legacy-cache-conf... */
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/* dtlb-write-access\000legacy cache\000Data TLB write accesses\000legacy-cache-con... */
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/* i-tlb-access\000legacy cache\000Instruction TLB read accesses\000legacy-cache-co... */
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/* i-tlb-load\000legacy cache\000Instruction TLB read accesses\000legacy-cache-conf... */
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/* i-tlb-loads-access\000legacy cache\000Instruction TLB read accesses\000legacy-ca... */
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/* i-tlb-loads-miss\000legacy cache\000Instruction TLB read misses\000legacy-cache-... */
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/* i-tlb-loads-misses\000legacy cache\000Instruction TLB read misses\000legacy-cach... */
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/* i-tlb-loads-ops\000legacy cache\000Instruction TLB read accesses\000legacy-cache... */
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/* i-tlb-loads-refs\000legacy cache\000Instruction TLB read accesses\000legacy-cach... */
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/* i-tlb-miss\000legacy cache\000Instruction TLB read misses\000legacy-cache-config... */
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/* i-tlb-misses\000legacy cache\000Instruction TLB read misses\000legacy-cache-conf... */
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/* i-tlb-read-access\000legacy cache\000Instruction TLB read accesses\000legacy-cac... */
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/* i-tlb-read-misses\000legacy cache\000Instruction TLB read misses\000legacy-cache... */
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/* i-tlb-read-refs\000legacy cache\000Instruction TLB read accesses\000legacy-cache... */
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/* i-tlb-reference\000legacy cache\000Instruction TLB read accesses\000legacy-cache... */
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/* i-tlb-refs\000legacy cache\000Instruction TLB read accesses\000legacy-cache-conf... */
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/* idle-cycles-backend\000legacy hardware\000Stalled cycles during retirement [This... */
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/* idle-cycles-frontend\000legacy hardware\000Stalled cycles during issue [This eve... */
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/* instruction-tlb\000legacy cache\000Instruction TLB read accesses\000legacy-cache... */
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/* instruction-tlb-access\000legacy cache\000Instruction TLB read accesses\000legac... */
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/* instruction-tlb-load\000legacy cache\000Instruction TLB read accesses\000legacy-... */
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/* instruction-tlb-load-access\000legacy cache\000Instruction TLB read accesses\000... */
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/* instruction-tlb-load-miss\000legacy cache\000Instruction TLB read misses\000lega... */
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/* instruction-tlb-load-misses\000legacy cache\000Instruction TLB read misses\000le... */
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/* instruction-tlb-load-ops\000legacy cache\000Instruction TLB read accesses\000leg... */
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/* instruction-tlb-load-reference\000legacy cache\000Instruction TLB read accesses\... */
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/* instruction-tlb-load-refs\000legacy cache\000Instruction TLB read accesses\000le... */
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/* instruction-tlb-loads\000legacy cache\000Instruction TLB read accesses\000legacy... */
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/* instruction-tlb-loads-access\000legacy cache\000Instruction TLB read accesses\00... */
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/* instruction-tlb-loads-miss\000legacy cache\000Instruction TLB read misses\000leg... */
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/* instruction-tlb-loads-misses\000legacy cache\000Instruction TLB read misses\000l... */
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/* instruction-tlb-loads-ops\000legacy cache\000Instruction TLB read accesses\000le... */
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/* instruction-tlb-loads-reference\000legacy cache\000Instruction TLB read accesses... */
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/* instruction-tlb-loads-refs\000legacy cache\000Instruction TLB read accesses\000l... */
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/* instruction-tlb-miss\000legacy cache\000Instruction TLB read misses\000legacy-ca... */
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/* instruction-tlb-misses\000legacy cache\000Instruction TLB read misses\000legacy-... */
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/* instruction-tlb-ops\000legacy cache\000Instruction TLB read accesses\000legacy-c... */
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/* instruction-tlb-read\000legacy cache\000Instruction TLB read accesses\000legacy-... */
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/* instruction-tlb-read-access\000legacy cache\000Instruction TLB read accesses\000... */
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/* instruction-tlb-read-miss\000legacy cache\000Instruction TLB read misses\000lega... */
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/* instruction-tlb-read-misses\000legacy cache\000Instruction TLB read misses\000le... */
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/* instruction-tlb-read-ops\000legacy cache\000Instruction TLB read accesses\000leg... */
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/* instruction-tlb-read-reference\000legacy cache\000Instruction TLB read accesses\... */
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/* instruction-tlb-read-refs\000legacy cache\000Instruction TLB read accesses\000le... */
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/* instruction-tlb-reference\000legacy cache\000Instruction TLB read accesses\000le... */
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/* instruction-tlb-refs\000legacy cache\000Instruction TLB read accesses\000legacy-... */
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/* instructions\000legacy hardware\000Retired instructions. Be careful, these can b... */
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/* itlb\000legacy cache\000Instruction TLB read accesses\000legacy-cache-config=4\0... */
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/* itlb-access\000legacy cache\000Instruction TLB read accesses\000legacy-cache-con... */
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/* itlb-load\000legacy cache\000Instruction TLB read accesses\000legacy-cache-confi... */
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/* itlb-load-access\000legacy cache\000Instruction TLB read accesses\000legacy-cach... */
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/* itlb-load-miss\000legacy cache\000Instruction TLB read misses\000legacy-cache-co... */
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/* itlb-load-misses\000legacy cache\000Instruction TLB read misses\000legacy-cache-... */
- { 93594 },
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/* itlb-load-ops\000legacy cache\000Instruction TLB read accesses\000legacy-cache-c... */
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/* itlb-load-reference\000legacy cache\000Instruction TLB read accesses\000legacy-c... */
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/* itlb-load-refs\000legacy cache\000Instruction TLB read accesses\000legacy-cache-... */
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/* l1i-speculative-read-access\000legacy cache\000Level 1 instruction cache prefetc... */
- { 47521 },
+ { 100733 },
/* l1i-speculative-read-miss\000legacy cache\000Level 1 instruction cache prefetch ... */
- { 47759 },
+ { 100852 },
/* l1i-speculative-read-misses\000legacy cache\000Level 1 instruction cache prefetc... */
- { 47640 },
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/* l1i-speculative-read-ops\000legacy cache\000Level 1 instruction cache prefetch a... */
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/* l1i-speculative-read-reference\000legacy cache\000Level 1 instruction cache pref... */
- { 47283 },
+ { 101204 },
/* l1i-speculative-read-refs\000legacy cache\000Level 1 instruction cache prefetch ... */
- { 47166 },
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/* l2\000legacy cache\000Level 2 (or higher) last level cache read accesses\000lega... */
- { 63212 },
+ { 101443 },
/* l2-access\000legacy cache\000Level 2 (or higher) last level cache read accesses\... */
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+ { 101540 },
/* l2-load\000legacy cache\000Level 2 (or higher) last level cache read accesses\00... */
- { 63309 },
+ { 101644 },
/* l2-load-access\000legacy cache\000Level 2 (or higher) last level cache read acce... */
- { 63736 },
+ { 101746 },
/* l2-load-miss\000legacy cache\000Level 2 (or higher) last level cache read misses... */
- { 63958 },
+ { 101855 },
/* l2-load-misses\000legacy cache\000Level 2 (or higher) last level cache read miss... */
- { 63845 },
+ { 101966 },
/* l2-load-ops\000legacy cache\000Level 2 (or higher) last level cache read accesse... */
- { 63630 },
+ { 102079 },
/* l2-load-reference\000legacy cache\000Level 2 (or higher) last level cache read a... */
- { 63518 },
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/* l2-load-refs\000legacy cache\000Level 2 (or higher) last level cache read access... */
- { 63411 },
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/* l2-loads\000legacy cache\000Level 2 (or higher) last level cache read accesses\0... */
- { 64069 },
+ { 102404 },
/* l2-loads-access\000legacy cache\000Level 2 (or higher) last level cache read acc... */
- { 64500 },
+ { 102507 },
/* l2-loads-miss\000legacy cache\000Level 2 (or higher) last level cache read misse... */
- { 64724 },
+ { 102617 },
/* l2-loads-misses\000legacy cache\000Level 2 (or higher) last level cache read mis... */
- { 64610 },
+ { 102729 },
/* l2-loads-ops\000legacy cache\000Level 2 (or higher) last level cache read access... */
- { 64393 },
+ { 102843 },
/* l2-loads-reference\000legacy cache\000Level 2 (or higher) last level cache read ... */
- { 64280 },
+ { 102950 },
/* l2-loads-refs\000legacy cache\000Level 2 (or higher) last level cache read acces... */
- { 64172 },
+ { 103063 },
/* l2-miss\000legacy cache\000Level 2 (or higher) last level cache read misses\000l... */
- { 71977 },
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/* l2-misses\000legacy cache\000Level 2 (or higher) last level cache read misses\00... */
- { 71869 },
+ { 103277 },
/* l2-ops\000legacy cache\000Level 2 (or higher) last level cache read accesses\000... */
- { 71664 },
+ { 103385 },
/* l2-prefetch\000legacy cache\000Level 2 (or higher) last level cache prefetch acc... */
- { 67985 },
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/* l2-prefetch-access\000legacy cache\000Level 2 (or higher) last level cache prefe... */
- { 68460 },
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/* l2-prefetch-miss\000legacy cache\000Level 2 (or higher) last level cache prefetc... */
- { 68702 },
+ { 103721 },
/* l2-prefetch-misses\000legacy cache\000Level 2 (or higher) last level cache prefe... */
- { 68581 },
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/* l2-prefetch-ops\000legacy cache\000Level 2 (or higher) last level cache prefetch... */
- { 68342 },
+ { 103961 },
/* l2-prefetch-reference\000legacy cache\000Level 2 (or higher) last level cache pr... */
- { 68218 },
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/* l2-prefetch-refs\000legacy cache\000Level 2 (or higher) last level cache prefetc... */
- { 68099 },
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/* l2-prefetches\000legacy cache\000Level 2 (or higher) last level cache prefetch a... */
- { 68821 },
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/* l2-prefetches-access\000legacy cache\000Level 2 (or higher) last level cache pre... */
- { 69304 },
+ { 104438 },
/* l2-prefetches-miss\000legacy cache\000Level 2 (or higher) last level cache prefe... */
- { 69550 },
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/* l2-prefetches-misses\000legacy cache\000Level 2 (or higher) last level cache pre... */
- { 69427 },
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/* l2-prefetches-ops\000legacy cache\000Level 2 (or higher) last level cache prefet... */
- { 69184 },
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/* l2-prefetches-reference\000legacy cache\000Level 2 (or higher) last level cache ... */
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/* l2-prefetches-refs\000legacy cache\000Level 2 (or higher) last level cache prefe... */
- { 68937 },
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/* l2-read\000legacy cache\000Level 2 (or higher) last level cache read accesses\00... */
- { 64836 },
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/* l2-read-access\000legacy cache\000Level 2 (or higher) last level cache read acce... */
- { 65263 },
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/* l2-read-miss\000legacy cache\000Level 2 (or higher) last level cache read misses... */
- { 65485 },
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/* l2-read-misses\000legacy cache\000Level 2 (or higher) last level cache read miss... */
- { 65372 },
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/* l2-read-ops\000legacy cache\000Level 2 (or higher) last level cache read accesse... */
- { 65157 },
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/* l2-read-reference\000legacy cache\000Level 2 (or higher) last level cache read a... */
- { 65045 },
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/* l2-read-refs\000legacy cache\000Level 2 (or higher) last level cache read access... */
- { 64938 },
+ { 105825 },
/* l2-reference\000legacy cache\000Level 2 (or higher) last level cache read access... */
- { 71557 },
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/* l2-refs\000legacy cache\000Level 2 (or higher) last level cache read accesses\00... */
- { 71455 },
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/* l2-speculative-load\000legacy cache\000Level 2 (or higher) last level cache pref... */
- { 70563 },
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/* l2-speculative-load-access\000legacy cache\000Level 2 (or higher) last level cac... */
- { 71070 },
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/* l2-speculative-load-miss\000legacy cache\000Level 2 (or higher) last level cache... */
- { 71328 },
+ { 106392 },
/* l2-speculative-load-misses\000legacy cache\000Level 2 (or higher) last level cac... */
- { 71199 },
+ { 106519 },
/* l2-speculative-load-ops\000legacy cache\000Level 2 (or higher) last level cache ... */
- { 70944 },
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/* l2-speculative-load-reference\000legacy cache\000Level 2 (or higher) last level ... */
- { 70812 },
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/* l2-speculative-load-refs\000legacy cache\000Level 2 (or higher) last level cache... */
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/* l2-speculative-read\000legacy cache\000Level 2 (or higher) last level cache pref... */
- { 69671 },
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/* l2-speculative-read-access\000legacy cache\000Level 2 (or higher) last level cac... */
- { 70178 },
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/* l2-speculative-read-miss\000legacy cache\000Level 2 (or higher) last level cache... */
- { 70436 },
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/* l2-speculative-read-misses\000legacy cache\000Level 2 (or higher) last level cac... */
- { 70307 },
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/* l2-speculative-read-ops\000legacy cache\000Level 2 (or higher) last level cache ... */
- { 70052 },
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/* l2-speculative-read-reference\000legacy cache\000Level 2 (or higher) last level ... */
- { 69920 },
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/* l2-speculative-read-refs\000legacy cache\000Level 2 (or higher) last level cache... */
- { 69793 },
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/* l2-store\000legacy cache\000Level 2 (or higher) last level cache write accesses\... */
- { 65596 },
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/* l2-store-access\000legacy cache\000Level 2 (or higher) last level cache write ac... */
- { 66047 },
+ { 108033 },
/* l2-store-miss\000legacy cache\000Level 2 (or higher) last level cache write miss... */
- { 66277 },
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/* l2-store-misses\000legacy cache\000Level 2 (or higher) last level cache write mi... */
- { 66162 },
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/* l2-store-ops\000legacy cache\000Level 2 (or higher) last level cache write acces... */
- { 65935 },
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/* l2-store-reference\000legacy cache\000Level 2 (or higher) last level cache write... */
- { 65817 },
+ { 108488 },
/* l2-store-refs\000legacy cache\000Level 2 (or higher) last level cache write acce... */
- { 65704 },
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/* l2-stores\000legacy cache\000Level 2 (or higher) last level cache write accesses... */
- { 66390 },
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/* l2-stores-access\000legacy cache\000Level 2 (or higher) last level cache write a... */
- { 66845 },
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/* l2-stores-miss\000legacy cache\000Level 2 (or higher) last level cache write mis... */
- { 67077 },
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/* l2-stores-misses\000legacy cache\000Level 2 (or higher) last level cache write m... */
- { 66961 },
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/* l2-stores-ops\000legacy cache\000Level 2 (or higher) last level cache write acce... */
- { 66732 },
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/* l2-stores-reference\000legacy cache\000Level 2 (or higher) last level cache writ... */
- { 66613 },
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/* l2-stores-refs\000legacy cache\000Level 2 (or higher) last level cache write acc... */
- { 66499 },
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/* l2-write\000legacy cache\000Level 2 (or higher) last level cache write accesses\... */
- { 67191 },
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/* l2-write-access\000legacy cache\000Level 2 (or higher) last level cache write ac... */
- { 67642 },
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/* l2-write-miss\000legacy cache\000Level 2 (or higher) last level cache write miss... */
- { 67872 },
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/* l2-write-misses\000legacy cache\000Level 2 (or higher) last level cache write mi... */
- { 67757 },
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/* l2-write-ops\000legacy cache\000Level 2 (or higher) last level cache write acces... */
- { 67530 },
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/* l2-write-reference\000legacy cache\000Level 2 (or higher) last level cache write... */
- { 67412 },
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/* l2-write-refs\000legacy cache\000Level 2 (or higher) last level cache write acce... */
- { 67299 },
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/* llc\000legacy cache\000Last level cache read accesses\000legacy-cache-config=2\0... */
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/* llc-access\000legacy cache\000Last level cache read accesses\000legacy-cache-con... */
- { 62951 },
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/* llc-load\000legacy cache\000Last level cache read accesses\000legacy-cache-confi... */
- { 55882 },
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/* llc-load-access\000legacy cache\000Last level cache read accesses\000legacy-cach... */
- { 56233 },
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/* llc-load-miss\000legacy cache\000Last level cache read misses\000legacy-cache-co... */
- { 56417 },
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/* llc-load-misses\000legacy cache\000Last level cache read misses\000legacy-cache-... */
- { 56323 },
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/* llc-load-ops\000legacy cache\000Last level cache read accesses\000legacy-cache-c... */
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/* llc-load-reference\000legacy cache\000Last level cache read accesses\000legacy-c... */
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/* llc-load-refs\000legacy cache\000Last level cache read accesses\000legacy-cache-... */
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/* llc-loads\000legacy cache\000Last level cache read accesses\000legacy-cache-conf... */
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/* llc-loads-access\000legacy cache\000Last level cache read accesses\000legacy-cac... */
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/* llc-loads-miss\000legacy cache\000Last level cache read misses\000legacy-cache-c... */
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/* llc-loads-misses\000legacy cache\000Last level cache read misses\000legacy-cache... */
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/* llc-loads-ops\000legacy cache\000Last level cache read accesses\000legacy-cache-... */
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/* llc-loads-reference\000legacy cache\000Last level cache read accesses\000legacy-... */
- { 56682 },
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/* llc-loads-refs\000legacy cache\000Last level cache read accesses\000legacy-cache... */
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/* llc-miss\000legacy cache\000Last level cache read misses\000legacy-cache-config=... */
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/* llc-misses\000legacy cache\000Last level cache read misses\000legacy-cache-confi... */
- { 63036 },
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/* llc-ops\000legacy cache\000Last level cache read accesses\000legacy-cache-config... */
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/* llc-prefetch\000legacy cache\000Last level cache prefetch accesses\000legacy-cac... */
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/* llc-prefetch-access\000legacy cache\000Last level cache prefetch accesses\000leg... */
- { 60159 },
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/* llc-prefetch-miss\000legacy cache\000Last level cache prefetch misses\000legacy-... */
- { 60363 },
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/* llc-prefetch-misses\000legacy cache\000Last level cache prefetch misses\000legac... */
- { 60261 },
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/* llc-prefetch-ops\000legacy cache\000Last level cache prefetch accesses\000legacy... */
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/* llc-prefetch-reference\000legacy cache\000Last level cache prefetch accesses\000... */
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/* llc-prefetch-refs\000legacy cache\000Last level cache prefetch accesses\000legac... */
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/* llc-prefetches\000legacy cache\000Last level cache prefetch accesses\000legacy-c... */
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/* llc-prefetches-access\000legacy cache\000Last level cache prefetch accesses\000l... */
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/* llc-prefetches-miss\000legacy cache\000Last level cache prefetch misses\000legac... */
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/* llc-prefetches-misses\000legacy cache\000Last level cache prefetch misses\000leg... */
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/* llc-prefetches-ops\000legacy cache\000Last level cache prefetch accesses\000lega... */
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/* llc-prefetches-reference\000legacy cache\000Last level cache prefetch accesses\0... */
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/* llc-prefetches-refs\000legacy cache\000Last level cache prefetch accesses\000leg... */
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/* llc-read\000legacy cache\000Last level cache read accesses\000legacy-cache-confi... */
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/* llc-read-access\000legacy cache\000Last level cache read accesses\000legacy-cach... */
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/* llc-read-miss\000legacy cache\000Last level cache read misses\000legacy-cache-co... */
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/* llc-read-misses\000legacy cache\000Last level cache read misses\000legacy-cache-... */
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/* llc-read-ops\000legacy cache\000Last level cache read accesses\000legacy-cache-c... */
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/* llc-read-reference\000legacy cache\000Last level cache read accesses\000legacy-c... */
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/* llc-read-refs\000legacy cache\000Last level cache read accesses\000legacy-cache-... */
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/* llc-reference\000legacy cache\000Last level cache read accesses\000legacy-cache-... */
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/* llc-refs\000legacy cache\000Last level cache read accesses\000legacy-cache-confi... */
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/* llc-speculative-load\000legacy cache\000Last level cache prefetch accesses\000le... */
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/* llc-speculative-load-access\000legacy cache\000Last level cache prefetch accesse... */
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/* llc-speculative-load-miss\000legacy cache\000Last level cache prefetch misses\00... */
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/* llc-speculative-load-misses\000legacy cache\000Last level cache prefetch misses\... */
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/* llc-speculative-load-ops\000legacy cache\000Last level cache prefetch accesses\0... */
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/* llc-speculative-load-reference\000legacy cache\000Last level cache prefetch acce... */
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/* llc-speculative-load-refs\000legacy cache\000Last level cache prefetch accesses\... */
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/* llc-speculative-read\000legacy cache\000Last level cache prefetch accesses\000le... */
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/* llc-speculative-read-access\000legacy cache\000Last level cache prefetch accesse... */
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/* llc-speculative-read-miss\000legacy cache\000Last level cache prefetch misses\00... */
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/* llc-speculative-read-misses\000legacy cache\000Last level cache prefetch misses\... */
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/* llc-speculative-read-ops\000legacy cache\000Last level cache prefetch accesses\0... */
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/* llc-speculative-read-reference\000legacy cache\000Last level cache prefetch acce... */
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/* llc-speculative-read-refs\000legacy cache\000Last level cache prefetch accesses\... */
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/* llc-store\000legacy cache\000Last level cache write accesses\000legacy-cache-con... */
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/* llc-store-access\000legacy cache\000Last level cache write accesses\000legacy-ca... */
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/* llc-store-miss\000legacy cache\000Last level cache write misses\000legacy-cache-... */
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/* llc-store-misses\000legacy cache\000Last level cache write misses\000legacy-cach... */
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/* llc-store-ops\000legacy cache\000Last level cache write accesses\000legacy-cache... */
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/* llc-store-reference\000legacy cache\000Last level cache write accesses\000legacy... */
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/* llc-store-refs\000legacy cache\000Last level cache write accesses\000legacy-cach... */
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/* llc-stores\000legacy cache\000Last level cache write accesses\000legacy-cache-co... */
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/* llc-stores-access\000legacy cache\000Last level cache write accesses\000legacy-c... */
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/* llc-stores-miss\000legacy cache\000Last level cache write misses\000legacy-cache... */
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/* llc-stores-misses\000legacy cache\000Last level cache write misses\000legacy-cac... */
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/* llc-stores-ops\000legacy cache\000Last level cache write accesses\000legacy-cach... */
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/* llc-stores-reference\000legacy cache\000Last level cache write accesses\000legac... */
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/* llc-stores-refs\000legacy cache\000Last level cache write accesses\000legacy-cac... */
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/* llc-write\000legacy cache\000Last level cache write accesses\000legacy-cache-con... */
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/* llc-write-access\000legacy cache\000Last level cache write accesses\000legacy-ca... */
- { 59474 },
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/* llc-write-miss\000legacy cache\000Last level cache write misses\000legacy-cache-... */
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/* llc-write-misses\000legacy cache\000Last level cache write misses\000legacy-cach... */
- { 59570 },
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/* llc-write-ops\000legacy cache\000Last level cache write accesses\000legacy-cache... */
- { 59381 },
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/* llc-write-reference\000legacy cache\000Last level cache write accesses\000legacy... */
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/* llc-write-refs\000legacy cache\000Last level cache write accesses\000legacy-cach... */
- { 59188 },
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/* node\000legacy cache\000Local memory read accesses\000legacy-cache-config=6\000\... */
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/* node-access\000legacy cache\000Local memory read accesses\000legacy-cache-config... */
- { 121053 },
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/* node-load\000legacy cache\000Local memory read accesses\000legacy-cache-config=6... */
- { 114203 },
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/* node-load-access\000legacy cache\000Local memory read accesses\000legacy-cache-c... */
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/* node-load-miss\000legacy cache\000Local memory read misses\000legacy-cache-confi... */
- { 114720 },
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/* node-load-misses\000legacy cache\000Local memory read misses\000legacy-cache-con... */
- { 114629 },
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/* node-load-ops\000legacy cache\000Local memory read accesses\000legacy-cache-conf... */
- { 114458 },
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/* node-load-reference\000legacy cache\000Local memory read accesses\000legacy-cach... */
- { 114368 },
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/* node-load-refs\000legacy cache\000Local memory read accesses\000legacy-cache-con... */
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/* node-loads\000legacy cache\000Local memory read accesses\000legacy-cache-config=... */
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/* node-loads-access\000legacy cache\000Local memory read accesses\000legacy-cache-... */
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/* node-loads-miss\000legacy cache\000Local memory read misses\000legacy-cache-conf... */
- { 115332 },
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/* node-loads-misses\000legacy cache\000Local memory read misses\000legacy-cache-co... */
- { 115240 },
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/* node-loads-ops\000legacy cache\000Local memory read accesses\000legacy-cache-con... */
- { 115067 },
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/* node-loads-reference\000legacy cache\000Local memory read accesses\000legacy-cac... */
- { 114976 },
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/* node-loads-refs\000legacy cache\000Local memory read accesses\000legacy-cache-co... */
- { 114890 },
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/* node-miss\000legacy cache\000Local memory read misses\000legacy-cache-config=0x1... */
- { 121221 },
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/* node-misses\000legacy cache\000Local memory read misses\000legacy-cache-config=0... */
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/* node-ops\000legacy cache\000Local memory read accesses\000legacy-cache-config=6\... */
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/* node-prefetch\000legacy cache\000Local memory prefetch accesses\000legacy-cache-... */
- { 117955 },
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/* node-prefetch-access\000legacy cache\000Local memory prefetch accesses\000legacy... */
- { 118342 },
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/* node-prefetch-miss\000legacy cache\000Local memory prefetch misses\000legacy-cac... */
- { 118540 },
+ { 119980 },
/* node-prefetch-misses\000legacy cache\000Local memory prefetch misses\000legacy-c... */
- { 118441 },
+ { 120077 },
/* node-prefetch-ops\000legacy cache\000Local memory prefetch accesses\000legacy-ca... */
- { 118246 },
+ { 120176 },
/* node-prefetch-reference\000legacy cache\000Local memory prefetch accesses\000leg... */
- { 118144 },
+ { 120272 },
/* node-prefetch-refs\000legacy cache\000Local memory prefetch accesses\000legacy-c... */
- { 118047 },
+ { 120374 },
/* node-prefetches\000legacy cache\000Local memory prefetch accesses\000legacy-cach... */
- { 118637 },
+ { 120471 },
/* node-prefetches-access\000legacy cache\000Local memory prefetch accesses\000lega... */
- { 119032 },
+ { 120565 },
/* node-prefetches-miss\000legacy cache\000Local memory prefetch misses\000legacy-c... */
- { 119234 },
+ { 120666 },
/* node-prefetches-misses\000legacy cache\000Local memory prefetch misses\000legacy... */
- { 119133 },
+ { 120765 },
/* node-prefetches-ops\000legacy cache\000Local memory prefetch accesses\000legacy-... */
- { 118934 },
+ { 120866 },
/* node-prefetches-reference\000legacy cache\000Local memory prefetch accesses\000l... */
- { 118830 },
+ { 120964 },
/* node-prefetches-refs\000legacy cache\000Local memory prefetch accesses\000legacy... */
- { 118731 },
+ { 121068 },
/* node-read\000legacy cache\000Local memory read accesses\000legacy-cache-config=6... */
- { 115422 },
+ { 121167 },
/* node-read-access\000legacy cache\000Local memory read accesses\000legacy-cache-c... */
- { 115761 },
+ { 121247 },
/* node-read-miss\000legacy cache\000Local memory read misses\000legacy-cache-confi... */
- { 115939 },
+ { 121334 },
/* node-read-misses\000legacy cache\000Local memory read misses\000legacy-cache-con... */
- { 115848 },
+ { 121423 },
/* node-read-ops\000legacy cache\000Local memory read accesses\000legacy-cache-conf... */
- { 115677 },
+ { 121514 },
/* node-read-reference\000legacy cache\000Local memory read accesses\000legacy-cach... */
- { 115587 },
+ { 121598 },
/* node-read-refs\000legacy cache\000Local memory read accesses\000legacy-cache-con... */
- { 115502 },
+ { 121688 },
/* node-reference\000legacy cache\000Local memory read accesses\000legacy-cache-con... */
- { 120889 },
+ { 121773 },
/* node-refs\000legacy cache\000Local memory read accesses\000legacy-cache-config=6... */
- { 120809 },
+ { 121858 },
/* node-speculative-load\000legacy cache\000Local memory prefetch accesses\000legac... */
- { 120071 },
+ { 121938 },
/* node-speculative-load-access\000legacy cache\000Local memory prefetch accesses\0... */
- { 120490 },
+ { 122038 },
/* node-speculative-load-miss\000legacy cache\000Local memory prefetch misses\000le... */
- { 120704 },
+ { 122145 },
/* node-speculative-load-misses\000legacy cache\000Local memory prefetch misses\000... */
- { 120597 },
+ { 122250 },
/* node-speculative-load-ops\000legacy cache\000Local memory prefetch accesses\000l... */
- { 120386 },
+ { 122357 },
/* node-speculative-load-reference\000legacy cache\000Local memory prefetch accesse... */
- { 120276 },
+ { 122461 },
/* node-speculative-load-refs\000legacy cache\000Local memory prefetch accesses\000... */
- { 120171 },
+ { 122571 },
/* node-speculative-read\000legacy cache\000Local memory prefetch accesses\000legac... */
- { 119333 },
+ { 122676 },
/* node-speculative-read-access\000legacy cache\000Local memory prefetch accesses\0... */
- { 119752 },
+ { 122776 },
/* node-speculative-read-miss\000legacy cache\000Local memory prefetch misses\000le... */
- { 119966 },
+ { 122883 },
/* node-speculative-read-misses\000legacy cache\000Local memory prefetch misses\000... */
- { 119859 },
+ { 122988 },
/* node-speculative-read-ops\000legacy cache\000Local memory prefetch accesses\000l... */
- { 119648 },
+ { 123095 },
/* node-speculative-read-reference\000legacy cache\000Local memory prefetch accesse... */
- { 119538 },
+ { 123199 },
/* node-speculative-read-refs\000legacy cache\000Local memory prefetch accesses\000... */
- { 119433 },
+ { 123309 },
/* node-store\000legacy cache\000Local memory write accesses\000legacy-cache-config... */
- { 116028 },
+ { 123414 },
/* node-store-access\000legacy cache\000Local memory write accesses\000legacy-cache... */
- { 116391 },
+ { 123500 },
/* node-store-miss\000legacy cache\000Local memory write misses\000legacy-cache-con... */
- { 116577 },
+ { 123593 },
/* node-store-misses\000legacy cache\000Local memory write misses\000legacy-cache-c... */
- { 116484 },
+ { 123684 },
/* node-store-ops\000legacy cache\000Local memory write accesses\000legacy-cache-co... */
- { 116301 },
+ { 123777 },
/* node-store-reference\000legacy cache\000Local memory write accesses\000legacy-ca... */
- { 116205 },
+ { 123867 },
/* node-store-refs\000legacy cache\000Local memory write accesses\000legacy-cache-c... */
- { 116114 },
+ { 123963 },
/* node-stores\000legacy cache\000Local memory write accesses\000legacy-cache-confi... */
- { 116668 },
+ { 124054 },
/* node-stores-access\000legacy cache\000Local memory write accesses\000legacy-cach... */
- { 117035 },
+ { 124141 },
/* node-stores-miss\000legacy cache\000Local memory write misses\000legacy-cache-co... */
- { 117223 },
+ { 124235 },
/* node-stores-misses\000legacy cache\000Local memory write misses\000legacy-cache-... */
- { 117129 },
+ { 124327 },
/* node-stores-ops\000legacy cache\000Local memory write accesses\000legacy-cache-c... */
- { 116944 },
+ { 124421 },
/* node-stores-reference\000legacy cache\000Local memory write accesses\000legacy-c... */
- { 116847 },
+ { 124512 },
/* node-stores-refs\000legacy cache\000Local memory write accesses\000legacy-cache-... */
- { 116755 },
+ { 124609 },
/* node-write\000legacy cache\000Local memory write accesses\000legacy-cache-config... */
- { 117315 },
+ { 124701 },
/* node-write-access\000legacy cache\000Local memory write accesses\000legacy-cache... */
- { 117678 },
+ { 124787 },
/* node-write-miss\000legacy cache\000Local memory write misses\000legacy-cache-con... */
- { 117864 },
+ { 124880 },
/* node-write-misses\000legacy cache\000Local memory write misses\000legacy-cache-c... */
- { 117771 },
+ { 124971 },
/* node-write-ops\000legacy cache\000Local memory write accesses\000legacy-cache-co... */
- { 117588 },
+ { 125064 },
/* node-write-reference\000legacy cache\000Local memory write accesses\000legacy-ca... */
- { 117492 },
+ { 125154 },
/* node-write-refs\000legacy cache\000Local memory write accesses\000legacy-cache-c... */
- { 117401 },
+ { 125250 },
/* ref-cycles\000legacy hardware\000Total cycles; not affected by CPU frequency sca... */
- { 123401 },
+ { 125963 },
/* stalled-cycles-backend\000legacy hardware\000Stalled cycles during retirement [T... */
- { 123095 },
+ { 126403 },
/* stalled-cycles-frontend\000legacy hardware\000Stalled cycles during issue [This ... */
- { 122795 },
+ { 126556 },
};
static const struct compact_pmu_event pmu_events__common_software[] = {
/* alignment-faults\000software\000Number of kernel handled memory alignment faults... */
- { 124564 },
+ { 0 },
/* bpf-output\000software\000An event used by BPF programs to write to the perf rin... */
- { 124863 },
+ { 2864 },
/* cgroup-switches\000software\000Number of context switches to a task in a differe... */
- { 124965 },
+ { 14585 },
/* context-switches\000software\000Number of context switches [This event is an ali... */
- { 123886 },
+ { 14688 },
/* cpu-clock\000software\000Per-CPU high-resolution timer based event\000config=0\0... */
- { 123522 },
+ { 14903 },
/* cpu-migrations\000software\000Number of times a process has migrated to a new CP... */
- { 124088 },
+ { 15151 },
/* cs\000software\000Number of context switches [This event is an alias of context-... */
- { 123987 },
+ { 15283 },
/* dummy\000software\000A placeholder event that doesn't count anything\000config=9... */
- { 124783 },
+ { 36684 },
/* emulation-faults\000software\000Number of kernel handled unimplemented instructi... */
- { 124656 },
+ { 36958 },
/* faults\000software\000Number of page faults [This event is an alias of page-faul... */
- { 123696 },
+ { 37197 },
/* major-faults\000software\000Number of major page faults. Major faults require I/... */
- { 124461 },
+ { 117820 },
/* migrations\000software\000Number of times a process has migrated to a new CPU [T... */
- { 124220 },
+ { 117923 },
/* minor-faults\000software\000Number of minor page faults. Minor faults don't requ... */
- { 124352 },
+ { 118055 },
/* page-faults\000software\000Number of page faults [This event is an alias of faul... */
- { 123791 },
+ { 125868 },
/* task-clock\000software\000Per-task high-resolution timer based event\000config=1... */
- { 123608 },
+ { 127253 },
};
static const struct compact_pmu_event pmu_events__common_tool[] = {
/* core_wide\000tool\0001 if not SMT, if SMT are events being gathered on all SMT t... */
- { 126206 },
+ { 14789 },
/* duration_time\000tool\000Wall clock interval time in nanoseconds\000config=1\000... */
- { 125073 },
+ { 36764 },
/* has_pmem\000tool\0001 if persistent memory installed otherwise 0\000config=4\000... */
- { 125287 },
+ { 37292 },
/* num_cores\000tool\000Number of cores. A core consists of 1 or more thread, with ... */
- { 125363 },
+ { 125341 },
/* num_cpus\000tool\000Number of logical Linux CPUs. There may be multiple such CPU... */
- { 125508 },
+ { 125486 },
/* num_cpus_online\000tool\000Number of online logical Linux CPUs. There may be mul... */
- { 125611 },
+ { 125589 },
/* num_dies\000tool\000Number of dies. Each die has 1 or more cores\000config=8\000... */
- { 125728 },
+ { 125706 },
/* num_packages\000tool\000Number of packages. Each package has 1 or more die\000co... */
- { 125804 },
+ { 125782 },
/* slots\000tool\000Number of functional units that in parallel can execute parts o... */
- { 125890 },
+ { 126177 },
/* smt_on\000tool\0001 if simultaneous multithreading (aka hyperthreading) is enabl... */
- { 126000 },
+ { 126287 },
/* system_time\000tool\000System/kernel time in nanoseconds\000config=3\000\00000\0... */
- { 125219 },
+ { 127002 },
/* system_tsc_freq\000tool\000The amount a Time Stamp Counter (TSC) increases per s... */
- { 126107 },
+ { 127070 },
/* target_cpu\000tool\0001 if CPUs being analyzed, 0 if threads/processes\000config... */
- { 126320 },
+ { 127169 },
/* user_time\000tool\000User (non-kernel) time in nanoseconds\000config=2\000\00000... */
- { 125149 },
+ { 127887 },
};
@@ -5187,55 +5187,55 @@ static const struct pmu_table_entry pmu_events__common[] = {
{
.entries = pmu_events__common_default_core,
.num_entries = ARRAY_SIZE(pmu_events__common_default_core),
- .pmu_name = { 0 /* default_core\000 */ },
+ .pmu_name = { 29669 /* default_core\000 */ },
},
{
.entries = pmu_events__common_software,
.num_entries = ARRAY_SIZE(pmu_events__common_software),
- .pmu_name = { 123513 /* software\000 */ },
+ .pmu_name = { 126394 /* software\000 */ },
},
{
.entries = pmu_events__common_tool,
.num_entries = ARRAY_SIZE(pmu_events__common_tool),
- .pmu_name = { 125068 /* tool\000 */ },
+ .pmu_name = { 127341 /* tool\000 */ },
},
};
static const struct compact_pmu_event pmu_metrics__common_default_core[] = {
/* CPUs_utilized\000Default\000(software@cpu\\-clock\\,name\\=cpu\\-clock@ if #targ... */
- { 127957 },
+ { 127980 },
/* backend_cycles_idle\000Default\000(stalled\\-cycles\\-backend / cpu\\-cycles if ... */
- { 129584 },
+ { 128971 },
/* branch_frequency\000Default\000branches / (software@cpu\\-clock\\,name\\=cpu\\-c... */
- { 129934 },
+ { 129145 },
/* branch_miss_rate\000Default\000branch\\-misses / branches\000branch_miss_rate > ... */
- { 130114 },
+ { 129325 },
/* cs_per_second\000Default\000software@context\\-switches\\,name\\=context\\-switc... */
- { 128143 },
+ { 129501 },
/* cycles_frequency\000Default\000cpu\\-cycles / (software@cpu\\-clock\\,name\\=cpu... */
- { 129758 },
+ { 129734 },
/* dtlb_miss_rate\000Default3\000dTLB\\-load\\-misses / dTLB\\-loads\000dtlb_miss_r... */
- { 130550 },
+ { 129975 },
/* frontend_cycles_idle\000Default\000(stalled\\-cycles\\-frontend / cpu\\-cycles i... */
- { 129405 },
+ { 130081 },
/* insn_per_cycle\000Default\000instructions / cpu\\-cycles\000insn_per_cycle < 1\0... */
- { 128867 },
+ { 130328 },
/* itlb_miss_rate\000Default3\000iTLB\\-load\\-misses / iTLB\\-loads\000itlb_miss_r... */
- { 130656 },
+ { 130441 },
/* l1_prefetch_miss_rate\000Default4\000L1\\-dcache\\-prefetch\\-misses / L1\\-dcac... */
- { 130762 },
+ { 130547 },
/* l1d_miss_rate\000Default2\000L1\\-dcache\\-load\\-misses / L1\\-dcache\\-loads\0... */
- { 130218 },
+ { 130695 },
/* l1i_miss_rate\000Default3\000L1\\-icache\\-load\\-misses / L1\\-icache\\-loads\0... */
- { 130435 },
+ { 130811 },
/* llc_miss_rate\000Default2\000LLC\\-load\\-misses / LLC\\-loads\000llc_miss_rate ... */
- { 130334 },
+ { 130926 },
/* migrations_per_second\000Default\000software@cpu\\-migrations\\,name\\=cpu\\-mig... */
- { 128376 },
+ { 131027 },
/* page_faults_per_second\000Default\000software@page\\-faults\\,name\\=page\\-faul... */
- { 128636 },
+ { 131287 },
/* stalled_cycles_per_instruction\000Default\000(max(stalled\\-cycles\\-frontend, s... */
- { 128980 },
+ { 131518 },
};
@@ -5243,47 +5243,47 @@ static const struct pmu_table_entry pmu_metrics__common[] = {
{
.entries = pmu_metrics__common_default_core,
.num_entries = ARRAY_SIZE(pmu_metrics__common_default_core),
- .pmu_name = { 0 /* default_core\000 */ },
+ .pmu_name = { 29669 /* default_core\000 */ },
},
};
static const struct compact_pmu_event pmu_events__test_soc_cpu_default_core[] = {
/* bp_l1_btb_correct\000branch\000L1 BTB Correction\000event=0x8a\000\00000\000\000... */
- { 126404 },
+ { 92 },
/* bp_l2_btb_correct\000branch\000L2 BTB Correction\000event=0x8b\000\00000\000\000... */
- { 126466 },
+ { 154 },
/* dispatch_blocked.any\000other\000Memory cluster signals to block micro-op dispat... */
- { 126728 },
+ { 29682 },
/* eist_trans\000other\000Number of Enhanced Intel SpeedStep(R) Technology (EIST) t... */
- { 126861 },
+ { 36840 },
/* l3_cache_rd\000cache\000L3 cache access, read\000event=0x40\000\00000\000\000\00... */
- { 126528 },
+ { 110314 },
/* segment_reg_loads.any\000other\000Number of segment register loads\000event=6,pe... */
- { 126626 },
+ { 126075 },
};
static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_ddrc[] = {
/* uncore_hisi_ddrc.flux_wcmd\000uncore\000DDRC write commands\000event=2\000\00000... */
- { 126994 },
+ { 127512 },
};
static const struct compact_pmu_event pmu_events__test_soc_cpu_hisi_sccl_l3c[] = {
/* uncore_hisi_l3c.rd_hit_cpipe\000uncore\000Total read hits\000event=7\000\00000\0... */
- { 127356 },
+ { 127582 },
};
static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_cbox[] = {
/* event-hyphen\000uncore\000UNC_CBO_HYPHEN\000event=0xe0\000\00000\000\000\000\000... */
- { 127230 },
+ { 37085 },
/* event-two-hyph\000uncore\000UNC_CBO_TWO_HYPH\000event=0xc0\000\00000\000\000\000... */
- { 127284 },
+ { 37139 },
/* unc_cbo_xsnp_response.miss_eviction\000uncore\000A cross-core snoop resulted fro... */
- { 127076 },
+ { 127346 },
};
static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc[] = {
/* uncore_imc.cache_hits\000uncore\000Total cache hits\000event=0x34\000\00000\000\... */
- { 127539 },
+ { 127661 },
};
static const struct compact_pmu_event pmu_events__test_soc_cpu_uncore_imc_free_running[] = {
/* uncore_imc_free_running.cache_miss\000uncore\000Total cache misses\000event=0x12... */
- { 127448 },
+ { 127750 },
};
@@ -5291,66 +5291,66 @@ static const struct pmu_table_entry pmu_events__test_soc_cpu[] = {
{
.entries = pmu_events__test_soc_cpu_default_core,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_default_core),
- .pmu_name = { 0 /* default_core\000 */ },
+ .pmu_name = { 29669 /* default_core\000 */ },
},
{
.entries = pmu_events__test_soc_cpu_hisi_sccl_ddrc,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_ddrc),
- .pmu_name = { 126979 /* hisi_sccl,ddrc\000 */ },
+ .pmu_name = { 37368 /* hisi_sccl,ddrc\000 */ },
},
{
.entries = pmu_events__test_soc_cpu_hisi_sccl_l3c,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_hisi_sccl_l3c),
- .pmu_name = { 127342 /* hisi_sccl,l3c\000 */ },
+ .pmu_name = { 37383 /* hisi_sccl,l3c\000 */ },
},
{
.entries = pmu_events__test_soc_cpu_uncore_cbox,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_cbox),
- .pmu_name = { 127064 /* uncore_cbox\000 */ },
+ .pmu_name = { 127500 /* uncore_cbox\000 */ },
},
{
.entries = pmu_events__test_soc_cpu_uncore_imc,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc),
- .pmu_name = { 127528 /* uncore_imc\000 */ },
+ .pmu_name = { 127650 /* uncore_imc\000 */ },
},
{
.entries = pmu_events__test_soc_cpu_uncore_imc_free_running,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_cpu_uncore_imc_free_running),
- .pmu_name = { 127424 /* uncore_imc_free_running\000 */ },
+ .pmu_name = { 127726 /* uncore_imc_free_running\000 */ },
},
};
static const struct compact_pmu_event pmu_metrics__test_soc_cpu_default_core[] = {
/* CPI\000\0001 / IPC\000\000\000\000\000\000\000\000000 */
- { 130910 },
+ { 127957 },
/* DCache_L2_All\000\000DCache_L2_All_Hits + DCache_L2_All_Miss\000\000\000\000\000... */
- { 131599 },
+ { 128166 },
/* DCache_L2_All_Hits\000\000l2_rqsts.demand_data_rd_hit + l2_rqsts.pf_hit + l2_rqs... */
- { 131369 },
+ { 128231 },
/* DCache_L2_All_Miss\000\000max(l2_rqsts.all_demand_data_rd - l2_rqsts.demand_data... */
- { 131464 },
+ { 128326 },
/* DCache_L2_Hits\000\000d_ratio(DCache_L2_All_Hits, DCache_L2_All)\000\000\000\000... */
- { 131664 },
+ { 128461 },
/* DCache_L2_Misses\000\000d_ratio(DCache_L2_All_Miss, DCache_L2_All)\000\000\000\0... */
- { 131733 },
+ { 128530 },
/* Frontend_Bound_SMT\000\000idq_uops_not_delivered.core / (4 * (cpu_clk_unhalted.t... */
- { 130997 },
+ { 128601 },
/* IPC\000group1\000inst_retired.any / cpu_clk_unhalted.thread\000\000\000\000\000\... */
- { 130933 },
+ { 128768 },
/* L1D_Cache_Fill_BW\000\00064 * l1d.replacement / 1e9 / duration_time\000\000\000\... */
- { 131871 },
+ { 128832 },
/* M1\000\000ipc + M2\000\000\000\000\000\000\000\000000 */
- { 131804 },
+ { 128904 },
/* M2\000\000ipc + M1\000\000\000\000\000\000\000\000000 */
- { 131827 },
+ { 128927 },
/* M3\000\0001 / M3\000\000\000\000\000\000\000\000000 */
- { 131850 },
+ { 128950 },
/* cache_miss_cycles\000group1\000dcache_miss_cpi + icache_miss_cycles\000\000\000\... */
- { 131297 },
+ { 129429 },
/* dcache_miss_cpi\000\000l1d\\-loads\\-misses / inst_retired.any\000\000\000\000\0... */
- { 131164 },
+ { 129910 },
/* icache_miss_cycles\000\000l1i\\-loads\\-misses / inst_retired.any\000\000\000\00... */
- { 131229 },
+ { 130260 },
};
@@ -5358,21 +5358,21 @@ static const struct pmu_table_entry pmu_metrics__test_soc_cpu[] = {
{
.entries = pmu_metrics__test_soc_cpu_default_core,
.num_entries = ARRAY_SIZE(pmu_metrics__test_soc_cpu_default_core),
- .pmu_name = { 0 /* default_core\000 */ },
+ .pmu_name = { 29669 /* default_core\000 */ },
},
};
static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ccn_pmu[] = {
/* sys_ccn_pmu.read_cycles\000uncore\000ccn read-cycles event\000config=0x2c\0000x0... */
- { 127718 },
+ { 126706 },
};
static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_cmn_pmu[] = {
/* sys_cmn_pmu.hnf_cache_miss\000uncore\000Counts total cache misses in first looku... */
- { 127814 },
+ { 126783 },
};
static const struct compact_pmu_event pmu_events__test_soc_sys_uncore_sys_ddr_pmu[] = {
/* sys_ddr_pmu.write_cycles\000uncore\000ddr write-cycles event\000event=0x2b\000v8... */
- { 127623 },
+ { 126926 },
};
@@ -5380,17 +5380,17 @@ static const struct pmu_table_entry pmu_events__test_soc_sys[] = {
{
.entries = pmu_events__test_soc_sys_uncore_sys_ccn_pmu,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ccn_pmu),
- .pmu_name = { 127699 /* uncore_sys_ccn_pmu\000 */ },
+ .pmu_name = { 127830 /* uncore_sys_ccn_pmu\000 */ },
},
{
.entries = pmu_events__test_soc_sys_uncore_sys_cmn_pmu,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_cmn_pmu),
- .pmu_name = { 127795 /* uncore_sys_cmn_pmu\000 */ },
+ .pmu_name = { 127849 /* uncore_sys_cmn_pmu\000 */ },
},
{
.entries = pmu_events__test_soc_sys_uncore_sys_ddr_pmu,
.num_entries = ARRAY_SIZE(pmu_events__test_soc_sys_uncore_sys_ddr_pmu),
- .pmu_name = { 127604 /* uncore_sys_ddr_pmu\000 */ },
+ .pmu_name = { 127868 /* uncore_sys_ddr_pmu\000 */ },
},
};
diff --git a/tools/perf/pmu-events/jevents.py b/tools/perf/pmu-events/jevents.py
index 0721c8b2551c..fae191272859 100755
--- a/tools/perf/pmu-events/jevents.py
+++ b/tools/perf/pmu-events/jevents.py
@@ -106,22 +106,16 @@ class BigCString:
strings: Set[bytes]
big_string: Sequence[str]
offsets: Dict[bytes, int]
- insert_number: int
- insert_point: Dict[bytes, int]
metrics: Set[bytes]
def __init__(self):
self.strings = set()
- self.insert_number = 0
- self.insert_point = {}
self.metrics = set()
def add(self, b: bytes, is_metric: bool) -> None:
"""Called to add NUL-terminated UTF-8 bytes to the big string."""
if b not in self.strings:
self.strings.add(b)
- self.insert_point[b] = self.insert_number
- self.insert_number += 1
if is_metric:
self.metrics.add(b)
@@ -162,8 +156,8 @@ class BigCString:
self.big_string = []
self.offsets = {}
- def string_cmp_key(b: bytes) -> Tuple[bool, int, bytes]:
- return (b in self.metrics, self.insert_point[b], b)
+ def string_cmp_key(b: bytes) -> Tuple[bool, bytes]:
+ return (b in self.metrics, b)
# Emit all strings that aren't folded in a sorted manner.
for b in sorted(self.strings, key=string_cmp_key):
--
2.56.1.703.gf848ed807c-goog
next prev parent reply other threads:[~2026-11-13 21:08 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-13 21:08 [PATCH 00/10] perf jevents: Block-indexed string compression and default JEVENTS_ARCH=all Ian Rogers
2026-11-13 21:08 ` [PATCH 01/10] perf jevents: Store raw bytes in BigCString instead of C-escaped strings Ian Rogers
2026-11-13 21:08 ` Ian Rogers [this message]
2026-11-13 21:08 ` [PATCH 03/10] perf jevents: Store PMU names as string literals in struct pmu_table_entry Ian Rogers
2026-11-13 21:08 ` [PATCH 04/10] perf jevents: Encapsulate big_c_string lookups behind pmu_events__get_string() Ian Rogers
2026-11-13 21:08 ` [PATCH 05/10] perf jevents: Add block-indexed string packing and --compress=zlib Ian Rogers
2026-11-13 21:08 ` [PATCH 06/10] perf jevents: Add --compress=lzma block compression backend Ian Rogers
2026-11-13 21:08 ` [PATCH 07/10] perf jevents: Add --compress=zstd " Ian Rogers
2026-11-13 21:08 ` [PATCH 08/10] perf build: Enable jevents string compression when available Ian Rogers
2026-11-13 21:08 ` [PATCH 09/10] perf tests pmu-events: Test metricgroup descriptions and concurrent lookups Ian Rogers
2026-11-13 21:08 ` [PATCH 10/10] perf build: Default JEVENTS_ARCH to all Ian Rogers
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