* [PATCH 1/2] clk: meson8b: expose every clock in the bindings
2017-07-31 11:38 [PATCH 0/2] clk: meson: expose clk ids Jerome Brunet
@ 2017-07-31 11:38 ` Jerome Brunet
2017-07-31 11:38 ` [PATCH 2/2] clk: meson-gxbb: expose almost " Jerome Brunet
` (2 subsequent siblings)
3 siblings, 0 replies; 6+ messages in thread
From: Jerome Brunet @ 2017-07-31 11:38 UTC (permalink / raw)
To: Neil Armstrong, Michael Turquette, Stephen Boyd, Carlo Caione,
Kevin Hilman, Arnd Bergmann, Olof Johansson
Cc: Jerome Brunet, linux-clk, linux-amlogic, linux-arm-kernel,
linux-kernel, devicetree
Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed (none on this
particular controller at the moment)
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/meson8b.h | 103 ++-----------------------------
include/dt-bindings/clock/meson8b-clkc.h | 70 +++++++++++++++++++++
2 files changed, 74 insertions(+), 99 deletions(-)
diff --git a/drivers/clk/meson/meson8b.h b/drivers/clk/meson/meson8b.h
index a687e02547dc..c139bb3273ca 100644
--- a/drivers/clk/meson/meson8b.h
+++ b/drivers/clk/meson/meson8b.h
@@ -60,107 +60,12 @@
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
- * Migrate them out of this header and into the DT header file when they need
- * to be exposed to client nodes in DT: include/dt-bindings/clock/meson8b-clkc.h
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
*/
-/* CLKID_UNUSED */
-/* CLKID_XTAL */
-/* CLKID_PLL_FIXED */
-/* CLKID_PLL_VID */
-/* CLKID_PLL_SYS */
-/* CLKID_FCLK_DIV2 */
-/* CLKID_FCLK_DIV3 */
-/* CLKID_FCLK_DIV4 */
-/* CLKID_FCLK_DIV5 */
-/* CLKID_FCLK_DIV7 */
-/* CLKID_CLK81 */
-/* CLKID_MALI */
-/* CLKID_CPUCLK */
-/* CLKID_ZERO */
-/* CLKID_MPEG_SEL */
-/* CLKID_MPEG_DIV */
-#define CLKID_DDR 16
-#define CLKID_DOS 17
-#define CLKID_ISA 18
-#define CLKID_PL301 19
-#define CLKID_PERIPHS 20
-#define CLKID_SPICC 21
-#define CLKID_I2C 22
-/* #define CLKID_SAR_ADC */
-#define CLKID_SMART_CARD 24
-/* #define CLKID_RNG0 */
-#define CLKID_UART0 26
-#define CLKID_SDHC 27
-#define CLKID_STREAM 28
-#define CLKID_ASYNC_FIFO 29
-/* #define CLKID_SDIO */
-#define CLKID_ABUF 31
-#define CLKID_HIU_IFACE 32
-#define CLKID_ASSIST_MISC 33
-#define CLKID_SPI 34
-#define CLKID_I2S_SPDIF 35
-/* #define CLKID_ETH */
-#define CLKID_DEMUX 37
-#define CLKID_AIU_GLUE 38
-#define CLKID_IEC958 39
-#define CLKID_I2S_OUT 40
-#define CLKID_AMCLK 41
-#define CLKID_AIFIFO2 42
-#define CLKID_MIXER 43
-#define CLKID_MIXER_IFACE 44
-#define CLKID_ADC 45
-#define CLKID_BLKMV 46
-#define CLKID_AIU 47
-#define CLKID_UART1 48
-#define CLKID_G2D 49
-/* #define CLKID_USB0 */
-/* #define CLKID_USB1 */
-#define CLKID_RESET 52
-#define CLKID_NAND 53
-#define CLKID_DOS_PARSER 54
-/* #define CLKID_USB */
-#define CLKID_VDIN1 56
-#define CLKID_AHB_ARB0 57
-#define CLKID_EFUSE 58
-#define CLKID_BOOT_ROM 59
-#define CLKID_AHB_DATA_BUS 60
-#define CLKID_AHB_CTRL_BUS 61
-#define CLKID_HDMI_INTR_SYNC 62
-#define CLKID_HDMI_PCLK 63
-/* CLKID_USB1_DDR_BRIDGE */
-/* CLKID_USB0_DDR_BRIDGE */
-#define CLKID_MMC_PCLK 66
-#define CLKID_DVIN 67
-#define CLKID_UART2 68
-/* #define CLKID_SANA */
-#define CLKID_VPU_INTR 70
-#define CLKID_SEC_AHB_AHB3_BRIDGE 71
-#define CLKID_CLK81_A9 72
-#define CLKID_VCLK2_VENCI0 73
-#define CLKID_VCLK2_VENCI1 74
-#define CLKID_VCLK2_VENCP0 75
-#define CLKID_VCLK2_VENCP1 76
-#define CLKID_GCLK_VENCI_INT 77
-#define CLKID_GCLK_VENCP_INT 78
-#define CLKID_DAC_CLK 79
-#define CLKID_AOCLK_GATE 80
-#define CLKID_IEC958_GATE 81
-#define CLKID_ENC480P 82
-#define CLKID_RNG1 83
-#define CLKID_GCLK_VENCL_INT 84
-#define CLKID_VCLK2_VENCLMCC 85
-#define CLKID_VCLK2_VENCL 86
-#define CLKID_VCLK2_OTHER 87
-#define CLKID_EDP 88
-#define CLKID_AO_MEDIA_CPU 89
-#define CLKID_AO_AHB_SRAM 90
-#define CLKID_AO_AHB_BUS 91
-#define CLKID_AO_IFACE 92
-#define CLKID_MPLL0 93
-#define CLKID_MPLL1 94
-#define CLKID_MPLL2 95
-
#define CLK_NR_CLKS 96
/* include the CLKIDs that have been made part of the stable DT binding */
diff --git a/include/dt-bindings/clock/meson8b-clkc.h b/include/dt-bindings/clock/meson8b-clkc.h
index e29227fb52a1..a9c0306330b6 100644
--- a/include/dt-bindings/clock/meson8b-clkc.h
+++ b/include/dt-bindings/clock/meson8b-clkc.h
@@ -21,15 +21,85 @@
#define CLKID_ZERO 13
#define CLKID_MPEG_SEL 14
#define CLKID_MPEG_DIV 15
+#define CLKID_DDR 16
+#define CLKID_DOS 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
+#define CLKID_SPICC 21
+#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
+#define CLKID_UART0 26
+#define CLKID_SDHC 27
+#define CLKID_STREAM 28
+#define CLKID_ASYNC_FIFO 29
#define CLKID_SDIO 30
+#define CLKID_ABUF 31
+#define CLKID_HIU_IFACE 32
+#define CLKID_ASSIST_MISC 33
+#define CLKID_SPI 34
+#define CLKID_I2S_SPDIF 35
#define CLKID_ETH 36
+#define CLKID_DEMUX 37
+#define CLKID_AIU_GLUE 38
+#define CLKID_IEC958 39
+#define CLKID_I2S_OUT 40
+#define CLKID_AMCLK 41
+#define CLKID_AIFIFO2 42
+#define CLKID_MIXER 43
+#define CLKID_MIXER_IFACE 44
+#define CLKID_ADC 45
+#define CLKID_BLKMV 46
+#define CLKID_AIU 47
+#define CLKID_UART1 48
+#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
+#define CLKID_RESET 52
+#define CLKID_NAND 53
+#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
+#define CLKID_VDIN1 56
+#define CLKID_AHB_ARB0 57
+#define CLKID_EFUSE 58
+#define CLKID_BOOT_ROM 59
+#define CLKID_AHB_DATA_BUS 60
+#define CLKID_AHB_CTRL_BUS 61
+#define CLKID_HDMI_INTR_SYNC 62
+#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_MMC_PCLK 66
+#define CLKID_DVIN 67
+#define CLKID_UART2 68
#define CLKID_SANA 69
+#define CLKID_VPU_INTR 70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A9 72
+#define CLKID_VCLK2_VENCI0 73
+#define CLKID_VCLK2_VENCI1 74
+#define CLKID_VCLK2_VENCP0 75
+#define CLKID_VCLK2_VENCP1 76
+#define CLKID_GCLK_VENCI_INT 77
+#define CLKID_GCLK_VENCP_INT 78
+#define CLKID_DAC_CLK 79
+#define CLKID_AOCLK_GATE 80
+#define CLKID_IEC958_GATE 81
+#define CLKID_ENC480P 82
+#define CLKID_RNG1 83
+#define CLKID_GCLK_VENCL_INT 84
+#define CLKID_VCLK2_VENCLMCC 85
+#define CLKID_VCLK2_VENCL 86
+#define CLKID_VCLK2_OTHER 87
+#define CLKID_EDP 88
+#define CLKID_AO_MEDIA_CPU 89
+#define CLKID_AO_AHB_SRAM 90
+#define CLKID_AO_AHB_BUS 91
+#define CLKID_AO_IFACE 92
+#define CLKID_MPLL0 93
+#define CLKID_MPLL1 94
+#define CLKID_MPLL2 95
#endif /* __MESON8B_CLKC_H */
--
2.9.4
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH 2/2] clk: meson-gxbb: expose almost every clock in the bindings
2017-07-31 11:38 [PATCH 0/2] clk: meson: expose clk ids Jerome Brunet
2017-07-31 11:38 ` [PATCH 1/2] clk: meson8b: expose every clock in the bindings Jerome Brunet
@ 2017-07-31 11:38 ` Jerome Brunet
2017-07-31 12:00 ` [PATCH 0/2] clk: meson: expose clk ids Neil Armstrong
2017-07-31 14:05 ` Arnd Bergmann
3 siblings, 0 replies; 6+ messages in thread
From: Jerome Brunet @ 2017-07-31 11:38 UTC (permalink / raw)
To: Neil Armstrong, Michael Turquette, Stephen Boyd, Carlo Caione,
Kevin Hilman, Arnd Bergmann, Olof Johansson
Cc: Jerome Brunet, linux-clk, linux-amlogic, linux-arm-kernel,
linux-kernel, devicetree
Expose all clocks which maybe used as DT bindings
Only clock ids internal the controller remain un-exposed
Signed-off-by: Jerome Brunet <jbrunet@baylibre.com>
---
drivers/clk/meson/gxbb.h | 117 ++--------------------------------
include/dt-bindings/clock/gxbb-clkc.h | 60 +++++++++++++++++
2 files changed, 67 insertions(+), 110 deletions(-)
diff --git a/drivers/clk/meson/gxbb.h b/drivers/clk/meson/gxbb.h
index d63e77e8433d..2c8986d3232c 100644
--- a/drivers/clk/meson/gxbb.h
+++ b/drivers/clk/meson/gxbb.h
@@ -167,130 +167,27 @@
* CLKID index values
*
* These indices are entirely contrived and do not map onto the hardware.
- * Migrate them out of this header and into the DT header file when they need
- * to be exposed to client nodes in DT: include/dt-bindings/clock/gxbb-clkc.h
+ * It has now been decided to expose everything by default in the DT header:
+ * include/dt-bindings/clock/gxbb-clkc.h. Only the clocks ids we don't want
+ * to expose, such as the internal muxes and dividers of composite clocks,
+ * will remain defined here.
*/
-#define CLKID_SYS_PLL 0
/* ID 1 is unused (it was used by the non-existing CLKID_CPUCLK before) */
-/* CLKID_HDMI_PLL */
-#define CLKID_FIXED_PLL 3
-/* CLKID_FCLK_DIV2 */
-/* CLKID_FCLK_DIV3 */
-/* CLKID_FCLK_DIV4 */
-#define CLKID_FCLK_DIV5 7
-#define CLKID_FCLK_DIV7 8
-/* CLKID_GP0_PLL */
#define CLKID_MPEG_SEL 10
#define CLKID_MPEG_DIV 11
-/* CLKID_CLK81 */
-#define CLKID_MPLL0 13
-#define CLKID_MPLL1 14
-/* CLKID_MPLL2 */
-#define CLKID_DDR 16
-#define CLKID_DOS 17
-#define CLKID_ISA 18
-#define CLKID_PL301 19
-#define CLKID_PERIPHS 20
-/* CLKID_SPICC */
-/* CLKID_I2C */
-/* #define CLKID_SAR_ADC */
-#define CLKID_SMART_CARD 24
-/* CLKID_RNG0 */
-/* CLKID_UART0 */
-#define CLKID_SDHC 27
-#define CLKID_STREAM 28
-#define CLKID_ASYNC_FIFO 29
-#define CLKID_SDIO 30
-#define CLKID_ABUF 31
-#define CLKID_HIU_IFACE 32
-#define CLKID_ASSIST_MISC 33
-/* CLKID_SPI */
-#define CLKID_I2S_SPDIF 35
-/* CLKID_ETH */
-#define CLKID_DEMUX 37
-/* CLKID_AIU_GLUE */
-/* CLKID_IEC958 */
-/* CLKID_I2S_OUT */
-#define CLKID_AMCLK 41
-#define CLKID_AIFIFO2 42
-#define CLKID_MIXER 43
-/* CLKID_MIXER_IFACE */
-#define CLKID_ADC 45
-#define CLKID_BLKMV 46
-/* CLKID_AIU */
-/* CLKID_UART1 */
-#define CLKID_G2D 49
-/* CLKID_USB0 */
-/* CLKID_USB1 */
-#define CLKID_RESET 52
-#define CLKID_NAND 53
-#define CLKID_DOS_PARSER 54
-/* CLKID_USB */
-#define CLKID_VDIN1 56
-#define CLKID_AHB_ARB0 57
-#define CLKID_EFUSE 58
-#define CLKID_BOOT_ROM 59
-#define CLKID_AHB_DATA_BUS 60
-#define CLKID_AHB_CTRL_BUS 61
-#define CLKID_HDMI_INTR_SYNC 62
-/* CLKID_HDMI_PCLK */
-/* CLKID_USB1_DDR_BRIDGE */
-/* CLKID_USB0_DDR_BRIDGE */
-#define CLKID_MMC_PCLK 66
-#define CLKID_DVIN 67
-/* CLKID_UART2 */
-/* #define CLKID_SANA */
-#define CLKID_VPU_INTR 70
-#define CLKID_SEC_AHB_AHB3_BRIDGE 71
-#define CLKID_CLK81_A53 72
-#define CLKID_VCLK2_VENCI0 73
-#define CLKID_VCLK2_VENCI1 74
-#define CLKID_VCLK2_VENCP0 75
-#define CLKID_VCLK2_VENCP1 76
-/* CLKID_GCLK_VENCI_INT0 */
-#define CLKID_GCLK_VENCI_INT 78
-#define CLKID_DAC_CLK 79
-/* CLKID_AOCLK_GATE */
-/* CLKID_IEC958_GATE */
-#define CLKID_ENC480P 82
-#define CLKID_RNG1 83
-#define CLKID_GCLK_VENCI_INT1 84
-#define CLKID_VCLK2_VENCLMCC 85
-#define CLKID_VCLK2_VENCL 86
-#define CLKID_VCLK_OTHER 87
-#define CLKID_EDP 88
-#define CLKID_AO_MEDIA_CPU 89
-#define CLKID_AO_AHB_SRAM 90
-#define CLKID_AO_AHB_BUS 91
-#define CLKID_AO_IFACE 92
-/* CLKID_AO_I2C */
-/* CLKID_SD_EMMC_A */
-/* CLKID_SD_EMMC_B */
-/* CLKID_SD_EMMC_C */
-/* CLKID_SAR_ADC_CLK */
-/* CLKID_SAR_ADC_SEL */
#define CLKID_SAR_ADC_DIV 99
-/* CLKID_MALI_0_SEL */
-#define CLKID_MALI_0_DIV 101
-/* CLKID_MALI_0 */
-/* CLKID_MALI_1_SEL */
-#define CLKID_MALI_1_DIV 104
-/* CLKID_MALI_1 */
-/* CLKID_MALI */
-/* CLKID_CTS_AMCLK */
+#define CLKID_MALI_0_DIV 101
+#define CLKID_MALI_1_DIV 104
#define CLKID_CTS_AMCLK_SEL 108
#define CLKID_CTS_AMCLK_DIV 109
-/* CLKID_CTS_MCLK_I958 */
#define CLKID_CTS_MCLK_I958_SEL 111
#define CLKID_CTS_MCLK_I958_DIV 112
-/* CLKID_CTS_I958 */
-#define CLKID_32K_CLK 114
#define CLKID_32K_CLK_SEL 115
#define CLKID_32K_CLK_DIV 116
#define NR_CLKS 117
-/* include the CLKIDs that have been made part of the stable DT binding */
+/* include the CLKIDs that have been made part of the DT binding */
#include <dt-bindings/clock/gxbb-clkc.h>
#endif /* __GXBB_H */
diff --git a/include/dt-bindings/clock/gxbb-clkc.h b/include/dt-bindings/clock/gxbb-clkc.h
index e3e9f7919c31..e07fea011ebd 100644
--- a/include/dt-bindings/clock/gxbb-clkc.h
+++ b/include/dt-bindings/clock/gxbb-clkc.h
@@ -5,37 +5,96 @@
#ifndef __GXBB_CLKC_H
#define __GXBB_CLKC_H
+#define CLKID_SYS_PLL 0
#define CLKID_HDMI_PLL 2
+#define CLKID_FIXED_PLL 3
#define CLKID_FCLK_DIV2 4
#define CLKID_FCLK_DIV3 5
#define CLKID_FCLK_DIV4 6
+#define CLKID_FCLK_DIV5 7
+#define CLKID_FCLK_DIV7 8
#define CLKID_GP0_PLL 9
#define CLKID_CLK81 12
+#define CLKID_MPLL0 13
+#define CLKID_MPLL1 14
#define CLKID_MPLL2 15
+#define CLKID_DDR 16
+#define CLKID_DOS 17
+#define CLKID_ISA 18
+#define CLKID_PL301 19
+#define CLKID_PERIPHS 20
#define CLKID_SPICC 21
#define CLKID_I2C 22
#define CLKID_SAR_ADC 23
+#define CLKID_SMART_CARD 24
#define CLKID_RNG0 25
#define CLKID_UART0 26
+#define CLKID_SDHC 27
+#define CLKID_STREAM 28
+#define CLKID_ASYNC_FIFO 29
+#define CLKID_SDIO 30
+#define CLKID_ABUF 31
+#define CLKID_HIU_IFACE 32
+#define CLKID_ASSIST_MISC 33
#define CLKID_SPI 34
#define CLKID_ETH 36
+#define CLKID_I2S_SPDIF 35
+#define CLKID_DEMUX 37
#define CLKID_AIU_GLUE 38
#define CLKID_IEC958 39
#define CLKID_I2S_OUT 40
+#define CLKID_AMCLK 41
+#define CLKID_AIFIFO2 42
+#define CLKID_MIXER 43
#define CLKID_MIXER_IFACE 44
+#define CLKID_ADC 45
+#define CLKID_BLKMV 46
#define CLKID_AIU 47
#define CLKID_UART1 48
+#define CLKID_G2D 49
#define CLKID_USB0 50
#define CLKID_USB1 51
+#define CLKID_RESET 52
+#define CLKID_NAND 53
+#define CLKID_DOS_PARSER 54
#define CLKID_USB 55
+#define CLKID_VDIN1 56
+#define CLKID_AHB_ARB0 57
+#define CLKID_EFUSE 58
+#define CLKID_BOOT_ROM 59
+#define CLKID_AHB_DATA_BUS 60
+#define CLKID_AHB_CTRL_BUS 61
+#define CLKID_HDMI_INTR_SYNC 62
#define CLKID_HDMI_PCLK 63
#define CLKID_USB1_DDR_BRIDGE 64
#define CLKID_USB0_DDR_BRIDGE 65
+#define CLKID_MMC_PCLK 66
+#define CLKID_DVIN 67
#define CLKID_UART2 68
#define CLKID_SANA 69
+#define CLKID_VPU_INTR 70
+#define CLKID_SEC_AHB_AHB3_BRIDGE 71
+#define CLKID_CLK81_A53 72
+#define CLKID_VCLK2_VENCI0 73
+#define CLKID_VCLK2_VENCI1 74
+#define CLKID_VCLK2_VENCP0 75
+#define CLKID_VCLK2_VENCP1 76
#define CLKID_GCLK_VENCI_INT0 77
+#define CLKID_GCLK_VENCI_INT 78
+#define CLKID_DAC_CLK 79
#define CLKID_AOCLK_GATE 80
#define CLKID_IEC958_GATE 81
+#define CLKID_ENC480P 82
+#define CLKID_RNG1 83
+#define CLKID_GCLK_VENCI_INT1 84
+#define CLKID_VCLK2_VENCLMCC 85
+#define CLKID_VCLK2_VENCL 86
+#define CLKID_VCLK_OTHER 87
+#define CLKID_EDP 88
+#define CLKID_AO_MEDIA_CPU 89
+#define CLKID_AO_AHB_SRAM 90
+#define CLKID_AO_AHB_BUS 91
+#define CLKID_AO_IFACE 92
#define CLKID_AO_I2C 93
#define CLKID_SD_EMMC_A 94
#define CLKID_SD_EMMC_B 95
@@ -50,5 +109,6 @@
#define CLKID_CTS_AMCLK 107
#define CLKID_CTS_MCLK_I958 110
#define CLKID_CTS_I958 113
+#define CLKID_32K_CLK 114
#endif /* __GXBB_CLKC_H */
--
2.9.4
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] clk: meson: expose clk ids
2017-07-31 11:38 [PATCH 0/2] clk: meson: expose clk ids Jerome Brunet
2017-07-31 11:38 ` [PATCH 1/2] clk: meson8b: expose every clock in the bindings Jerome Brunet
2017-07-31 11:38 ` [PATCH 2/2] clk: meson-gxbb: expose almost " Jerome Brunet
@ 2017-07-31 12:00 ` Neil Armstrong
2017-07-31 14:05 ` Arnd Bergmann
3 siblings, 0 replies; 6+ messages in thread
From: Neil Armstrong @ 2017-07-31 12:00 UTC (permalink / raw)
To: Jerome Brunet, Michael Turquette, Stephen Boyd, Carlo Caione,
Kevin Hilman, Arnd Bergmann, Olof Johansson
Cc: linux-clk, linux-amlogic, linux-arm-kernel, linux-kernel, devicetree
On 07/31/2017 01:38 PM, Jerome Brunet wrote:
> In previous cycles, concerns have been raised about the way clocks are
> exposed for the meson clock controller, only when validated and required
> in DT.
>
> Instead, this patchset expose all the known clocks which may be needed in
> DT later on. The clocks left out are internal clocks which should never be
> used directly in DT. These are mostly internal muxes and dividers of
> composite clocks.
>
> While this should reduce the patch flow on the related header files, It
> won't stop it completely. There are still many clocks we don't know about
> yet. We tend discover a few in every cycle.
>
> This patchset depends on these fixes [0] to avoid issues when adding new
> clk ids.
>
> [0]: https://lkml.kernel.org/r/20170727161755.10393-1-jbrunet@baylibre.com
>
> Jerome Brunet (2):
> clk: meson8b: expose every clock in the bindings
> clk: meson-gxbb: expose almost every clock in the bindings
>
> drivers/clk/meson/gxbb.h | 117 ++-----------------------------
> drivers/clk/meson/meson8b.h | 103 ++-------------------------
> include/dt-bindings/clock/gxbb-clkc.h | 60 ++++++++++++++++
> include/dt-bindings/clock/meson8b-clkc.h | 70 ++++++++++++++++++
> 4 files changed, 141 insertions(+), 209 deletions(-)
>
Acked-by: Neil Armstrong <narmstrong@baylibre.com>
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH 0/2] clk: meson: expose clk ids
2017-07-31 11:38 [PATCH 0/2] clk: meson: expose clk ids Jerome Brunet
` (2 preceding siblings ...)
2017-07-31 12:00 ` [PATCH 0/2] clk: meson: expose clk ids Neil Armstrong
@ 2017-07-31 14:05 ` Arnd Bergmann
2017-08-01 12:00 ` Neil Armstrong
3 siblings, 1 reply; 6+ messages in thread
From: Arnd Bergmann @ 2017-07-31 14:05 UTC (permalink / raw)
To: Jerome Brunet
Cc: Neil Armstrong, Michael Turquette, Stephen Boyd, Carlo Caione,
Kevin Hilman, Olof Johansson, linux-clk,
open list:ARM/Amlogic Meson SoC support, Linux ARM,
Linux Kernel Mailing List, devicetree
On Mon, Jul 31, 2017 at 1:38 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
> In previous cycles, concerns have been raised about the way clocks are
> exposed for the meson clock controller, only when validated and required
> in DT.
>
> Instead, this patchset expose all the known clocks which may be needed in
> DT later on. The clocks left out are internal clocks which should never be
> used directly in DT. These are mostly internal muxes and dividers of
> composite clocks.
>
> While this should reduce the patch flow on the related header files, It
> won't stop it completely. There are still many clocks we don't know about
> yet. We tend discover a few in every cycle.
>
> This patchset depends on these fixes [0] to avoid issues when adding new
> clk ids.
>
> [0]: https://lkml.kernel.org/r/20170727161755.10393-1-jbrunet@baylibre.com
Thanks a lot!
Acked-by: Arnd Bergmann <arnd@arndb.de>
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH 0/2] clk: meson: expose clk ids
2017-07-31 14:05 ` Arnd Bergmann
@ 2017-08-01 12:00 ` Neil Armstrong
0 siblings, 0 replies; 6+ messages in thread
From: Neil Armstrong @ 2017-08-01 12:00 UTC (permalink / raw)
To: Arnd Bergmann, Jerome Brunet
Cc: Michael Turquette, Stephen Boyd, Carlo Caione, Kevin Hilman,
Olof Johansson, linux-clk,
open list:ARM/Amlogic Meson SoC support, Linux ARM,
Linux Kernel Mailing List, devicetree
On 07/31/2017 04:05 PM, Arnd Bergmann wrote:
> On Mon, Jul 31, 2017 at 1:38 PM, Jerome Brunet <jbrunet@baylibre.com> wrote:
>> In previous cycles, concerns have been raised about the way clocks are
>> exposed for the meson clock controller, only when validated and required
>> in DT.
>>
>> Instead, this patchset expose all the known clocks which may be needed in
>> DT later on. The clocks left out are internal clocks which should never be
>> used directly in DT. These are mostly internal muxes and dividers of
>> composite clocks.
>>
>> While this should reduce the patch flow on the related header files, It
>> won't stop it completely. There are still many clocks we don't know about
>> yet. We tend discover a few in every cycle.
>>
>> This patchset depends on these fixes [0] to avoid issues when adding new
>> clk ids.
>>
>> [0]: https://lkml.kernel.org/r/20170727161755.10393-1-jbrunet@baylibre.com
>
> Thanks a lot!
>
> Acked-by: Arnd Bergmann <arnd@arndb.de>
>
Applied to clk-meson's next/headers with arnd's ack.
^ permalink raw reply [flat|nested] 6+ messages in thread