[PATCH 3/5] perf/amd/ibs: Limit the max EILVT register count for AMD family 0x10

["Naveen N Rao (AMD)" <naveen@kernel.org>]

For AMD family 0x10, EILVT offsets are not assigned by BIOS and is
instead assigned by picking the next available EILVT offset.  Use the
maximum EILVT count for family 0x10 (APIC_EILVT_NR_AMD_10H) rather than
an arbitrary maximum EILVT count when looking for the next available
EILVT offset.

Signed-off-by: Naveen N Rao (AMD) <naveen@kernel.org>
Tested-by: Manali Shukla <manali.shukla@amd.com>
---
 arch/x86/events/amd/ibs.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

diff --git a/arch/x86/events/amd/ibs.c b/arch/x86/events/amd/ibs.c
index e0bd5051db2a..61d14cbdda49 100644
--- a/arch/x86/events/amd/ibs.c
+++ b/arch/x86/events/amd/ibs.c
@@ -1838,13 +1838,13 @@ static void force_ibs_eilvt_setup(void)
 
 	preempt_disable();
 	/* find the next free available EILVT entry, skip offset 0 */
-	for (offset = 1; offset < APIC_EILVT_NR_MAX; offset++) {
+	for (offset = 1; offset < APIC_EILVT_NR_AMD_10H; offset++) {
 		if (get_eilvt(offset))
 			break;
 	}
 	preempt_enable();
 
-	if (offset == APIC_EILVT_NR_MAX) {
+	if (offset == APIC_EILVT_NR_AMD_10H) {
 		pr_debug("No EILVT entry available\n");
 		return;
 	}
-- 
2.53.0