From: Paul Cercueil <paul@crapouillou.net>
To: Florian Fainelli <f.fainelli@gmail.com>, linux-mips@vger.kernel.org
Cc: "周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Paul Burton" <paulburton@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
hns@goldelico.com, paul@boddie.org.uk
Subject: Re: [PATCH v2 3/3] MIPS: CI20: Enable SMP with two CPUs
Date: Tue, 10 Nov 2026 16:31:40 +0100 [thread overview]
Message-ID: <21144503d8b588df45a1f5e2c3a756fd0c3b67a0.camel@crapouillou.net> (raw)
In-Reply-To: <20261110043131.1985993-4-f.fainelli@gmail.com>
Le lundi 09 novembre 2026 à 20:31 -0800, Florian Fainelli a écrit :
> From: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
>
> Enable both JZ4780 cores now that the generic Ingenic platform provides
> secondary CPU reset and mailbox support. The existing device tree
> already reserves TCU channels for both per-CPU clock events.
>
> Link: https://lists.openwall.net/linux-kernel/2020/05/19/739
> Signed-off-by: 周琰杰 (Zhou Yanjie) <zhouyanjie@wanyeetech.com>
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Paul Cercueil <paul@crapouillou.net>
Cheers,
-Paul
> ---
> arch/mips/configs/ci20_defconfig | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/mips/configs/ci20_defconfig
> b/arch/mips/configs/ci20_defconfig
> index 90536cab417e..09d65094b1bd 100644
> --- a/arch/mips/configs/ci20_defconfig
> +++ b/arch/mips/configs/ci20_defconfig
> @@ -22,6 +22,8 @@ CONFIG_EXPERT=y
> CONFIG_MACH_INGENIC_SOC=y
> CONFIG_JZ4780_CI20=y
> CONFIG_HIGHMEM=y
> +CONFIG_SMP=y
> +CONFIG_NR_CPUS=2
> CONFIG_HZ_100=y
> # CONFIG_SUSPEND is not set
> # CONFIG_SECCOMP is not set
next prev parent reply other threads:[~2026-11-10 15:31 UTC|newest]
Thread overview: 9+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 4:31 [PATCH v2 0/3] " Florian Fainelli
2026-11-10 4:31 ` [PATCH v2 1/3] clk: ingenic: Poll JZ4780 CPU1 power status atomically Florian Fainelli
2026-11-10 4:31 ` [PATCH v2 2/3] MIPS: Ingenic: Add XBurst SMP support Florian Fainelli
2026-11-10 15:30 ` Paul Cercueil
2026-11-10 4:31 ` [PATCH v2 3/3] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
2026-11-10 15:31 ` Paul Cercueil [this message]
2026-11-10 15:44 ` [PATCH v2 0/3] " Paul Cercueil
2026-11-10 17:14 ` Florian Fainelli
2026-11-10 18:11 ` Paul Cercueil
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