From: Paul Cercueil <paul@crapouillou.net>
To: Florian Fainelli <f.fainelli@gmail.com>, linux-mips@vger.kernel.org
Cc: "Thomas Bogendoerfer" <tsbogend@alpha.franken.de>,
"Paul Burton" <paulburton@kernel.org>,
"Stephen Boyd" <sboyd@kernel.org>,
"Brian Masney" <bmasney+clk@redhat.com>,
"Jerome Brunet" <jbrunet+clk@baylibre.com>,
"周琰杰 (Zhou Yanjie)" <zhouyanjie@wanyeetech.com>,
"Jiaxun Yang" <jiaxun.yang@flygoat.com>,
"open list" <linux-kernel@vger.kernel.org>,
"open list:COMMON CLK FRAMEWORK" <linux-clk@vger.kernel.org>,
hns@goldelico.com, paul@boddie.org.uk
Subject: Re: [PATCH v2 0/3] MIPS: CI20: Enable SMP with two CPUs
Date: Tue, 10 Nov 2026 16:44:41 +0100 [thread overview]
Message-ID: <d40bcc5d7742025db9a67af5c77796745e284e45.camel@crapouillou.net> (raw)
In-Reply-To: <20261110043131.1985993-1-f.fainelli@gmail.com>
Hi Florian,
Le lundi 09 novembre 2026 à 20:31 -0800, Florian Fainelli a écrit :
> This patch series resurrects SMP support for the CI20 board. This was
> submitted back in 2020 by Zhou Yanjie.
>
> Changes in v2:
>
> • Moved SMP sources to arch/mips/ingenic/ and the header to
> arch/mips/include/asm/
> • Removed CONFIG_MIPS_INGENIC_SMP, using CONFIG_MACH_JZ4780 and CONFIG_SMP
> directly
> • Renamed JZ4780-specific SMP symbols to XBurst names
> • Changed CPU enumeration to assign consecutive logical IDs and removed the
> explicit two-core limit
> • Changed mailbox IRQ allocation failure from panic to logging and returning
> • Shortened commit descriptions, removed Codex attribution, and adjusted
> source credits and sign-offs
> • Kept the clock polling patch and CI20 defconfig changes unchanged,
> added Paul's R-b for patch #1
> • Updated the kernel baseline to include additional upstream fixes
You should also have a changelog per-patch, in each patch's header.
Your patch [1/3] has a Fixes: tag but does not Cc stable@vger.kernel.org, so
you'll have to send a v3.
I reviewed [2/3] and it looks good to me, but I'm a bit concerned about
Nikolaus' reported issue.
Thomas, if you can wait a few days, I can test it on my CI20 and if it works
report back with a Tested-by: tag.
Cheers,
-Paul
>
> Florian Fainelli (1):
> clk: ingenic: Poll JZ4780 CPU1 power status atomically
>
> 周琰杰 (Zhou Yanjie) (2):
> MIPS: Ingenic: Add XBurst SMP support
> MIPS: CI20: Enable SMP with two CPUs
>
> MAINTAINERS | 3 +-
> arch/mips/Kbuild | 1 +
> arch/mips/configs/ci20_defconfig | 2 +
> arch/mips/generic/init.c | 3 +
> arch/mips/include/asm/ingenic-smp.h | 20 +++
> arch/mips/ingenic/Kconfig | 2 +
> arch/mips/ingenic/Makefile | 5 +
> arch/mips/ingenic/ingenic-smp-entry.S | 54 ++++++
> arch/mips/ingenic/ingenic-smp.c | 247 ++++++++++++++++++++++++++
> arch/mips/kernel/idle.c | 26 ++-
> drivers/clk/ingenic/jz4780-cgu.c | 2 +-
> 11 files changed, 362 insertions(+), 3 deletions(-)
> create mode 100644 arch/mips/include/asm/ingenic-smp.h
> create mode 100644 arch/mips/ingenic/Makefile
> create mode 100644 arch/mips/ingenic/ingenic-smp-entry.S
> create mode 100644 arch/mips/ingenic/ingenic-smp.c
prev parent reply other threads:[~2026-11-10 15:44 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-11-10 4:31 Florian Fainelli
2026-11-10 4:31 ` [PATCH v2 1/3] clk: ingenic: Poll JZ4780 CPU1 power status atomically Florian Fainelli
2026-11-10 4:31 ` [PATCH v2 2/3] MIPS: Ingenic: Add XBurst SMP support Florian Fainelli
2026-11-10 15:30 ` Paul Cercueil
2026-11-10 4:31 ` [PATCH v2 3/3] MIPS: CI20: Enable SMP with two CPUs Florian Fainelli
2026-11-10 15:31 ` Paul Cercueil
2026-11-10 15:44 ` Paul Cercueil [this message]
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