[PATCH v1] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

[PATCH v1] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

[Delphine CC Chiu]

From: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>

Revise quad mode to dual mode to avoid WP pin influnece the SPI.

Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
---
 .../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
 1 file changed, 5 insertions(+), 3 deletions(-)

diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
index 98477792aa00..3073ade6d77c 100644
--- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
+++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
@@ -105,15 +105,17 @@ flash@0 {
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc";
-		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
-#include "openbmc-flash-layout-64.dtsi"
+#include "openbmc-flash-layout-128.dtsi"
 	};
 	flash@1 {
 		status = "okay";
 		m25p,fast-read;
 		label = "bmc2";
-		spi-rx-bus-width = <4>;
+		spi-tx-bus-width = <2>;
+		spi-rx-bus-width = <2>;
 		spi-max-frequency = <50000000>;
 	};
 };
-- 
2.25.1

Re: [PATCH v1] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

[Andrew Jeffery]

On Tue, 2024-09-10 at 13:13 +0800, Delphine CC Chiu wrote:
> From: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
> 
> Revise quad mode to dual mode to avoid WP pin influnece the SPI.
> 
> Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
> Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> ---
>  .../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8 +++++---
>  1 file changed, 5 insertions(+), 3 deletions(-)
> 
> diff --git a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> index 98477792aa00..3073ade6d77c 100644
> --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> @@ -105,15 +105,17 @@ flash@0 {
>  		status = "okay";
>  		m25p,fast-read;
>  		label = "bmc";
> -		spi-rx-bus-width = <4>;
> +		spi-tx-bus-width = <2>;
> +		spi-rx-bus-width = <2>;
>  		spi-max-frequency = <50000000>;
> -#include "openbmc-flash-layout-64.dtsi"
> +#include "openbmc-flash-layout-128.dtsi"

This is a bit more drastic than changing the bus mode.

Can you please split that out to a separate change with some
justification in the commit message? For instance, was the chip changed
too? Or were you using the 64M layout or a 128M chip the whole time?

Andrew

RE: [PATCH v1] ARM: dts: aspeed: yosemite4: Revise quad mode to dual mode

[Delphine_CC_Chiu/WYHQ/Wiwynn]

> -----Original Message-----
> From: Andrew Jeffery <andrew@codeconstruct.com.au>
> Sent: Thursday, September 12, 2024 10:17 AM
> To: Delphine_CC_Chiu/WYHQ/Wiwynn <Delphine_CC_Chiu@wiwynn.com>;
> patrick@stwcx.xyz; Rob Herring <robh@kernel.org>; Krzysztof Kozlowski
> <krzk+dt@kernel.org>; Conor Dooley <conor+dt@kernel.org>; Joel Stanley
> <joel@jms.id.au>
> Cc: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>;
> devicetree@vger.kernel.org; linux-arm-kernel@lists.infradead.org;
> linux-aspeed@lists.ozlabs.org; linux-kernel@vger.kernel.org
> Subject: Re: [PATCH v1] ARM: dts: aspeed: yosemite4: Revise quad mode to
> dual mode
> 
>  [External Sender]
> 
>  [External Sender]
> 
> On Tue, 2024-09-10 at 13:13 +0800, Delphine CC Chiu wrote:
> > From: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
> >
> > Revise quad mode to dual mode to avoid WP pin influnece the SPI.
> >
> > Signed-off-by: Ricky CX Wu <ricky.cx.wu.wiwynn@gmail.com>
> > Signed-off-by: Delphine CC Chiu <Delphine_CC_Chiu@wiwynn.com>
> > ---
> >  .../arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts | 8
> > +++++---
> >  1 file changed, 5 insertions(+), 3 deletions(-)
> >
> > diff --git
> > a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> > b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> > index 98477792aa00..3073ade6d77c 100644
> > --- a/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> > +++ b/arch/arm/boot/dts/aspeed/aspeed-bmc-facebook-yosemite4.dts
> > @@ -105,15 +105,17 @@ flash@0 {
> >               status = "okay";
> >               m25p,fast-read;
> >               label = "bmc";
> > -             spi-rx-bus-width = <4>;
> > +             spi-tx-bus-width = <2>;
> > +             spi-rx-bus-width = <2>;
> >               spi-max-frequency = <50000000>; -#include
> > "openbmc-flash-layout-64.dtsi"
> > +#include "openbmc-flash-layout-128.dtsi"
> 
> This is a bit more drastic than changing the bus mode.
> 
> Can you please split that out to a separate change with some justification in
> the commit message? For instance, was the chip changed too? Or were you
> using the 64M layout or a 128M chip the whole time?
> 
> Andrew
I'll split the patch in v2. Thanks!