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From: Pu Lehui <pulehui@huawei.com>
To: Kuan-Wei Chiu <visitorckw@gmail.com>, <ast@kernel.org>,
	<daniel@iogearbox.net>, <andrii@kernel.org>, <eddyz87@gmail.com>,
	<memxor@gmail.com>, <luke.r.nels@gmail.com>, <xi.wang@gmail.com>,
	<pjw@kernel.org>, <palmer@dabbelt.com>, <aou@eecs.berkeley.edu>
Cc: <martin.lau@linux.dev>, <song@kernel.org>,
	<yonghong.song@linux.dev>, <jolsa@kernel.org>, <alex@ghiti.fr>,
	<jserv@ccns.ncku.edu.tw>, <eleanor15x@gmail.com>,
	<marscheng@google.com>, <bpf@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH bpf-next v2 0/3] riscv, bpf: Fix signed operations and add 32 bit atomics
Date: Tue, 16 Jun 2026 09:41:21 +0800	[thread overview]
Message-ID: <216ee1df-2945-4266-9c70-ebcd36faeb7f@huawei.com> (raw)
In-Reply-To: <ajAlwK990NFUAMwq@google.com>



On 2026/6/16 0:18, Kuan-Wei Chiu wrote:
> Hi,
> 
> On Mon, May 11, 2026 at 10:16:45PM +0000, Kuan-Wei Chiu wrote:
>> Fix miscompiled signed operations and expands 32 bit atomic support in
>> the RV32 BPF JIT.
>>
>> The current implementation ignores the instruction offset field used by
>> the bpf instruction set to specify BPF_SDIV/BPF_SMOD and BPF_MOVSX.
>> This causes these operations to be treated as unsigned or
>> zero-extended, leading to test_bpf failures. Fix this by checking the
>> offset and emitting the correct instructions.
>>
>> Additionally, we leverage the mandatory A extension to natively support
>> 32 bit bpf atomics (and, or, xor, xchg) by mapping them directly to
>> amo*.w instructions. BPF_CMPXCHG continues to fall back to the
>> interpreter.
>>
>> As a result, test_bpf.ko now runs with 0 failures, and the total number
>> of successfully JIT'ed test cases increases from 843 to 902.
> 
> Is there anything else I need to do for this patchset to land?

Hi Kuan-wei, it seems Luke and Xi haven't been as active in the 
community for a while, I'll make time to cover the review and testing 
for this.

Regards,
Lehui

> 
> Regards,
> Kuan-wei
> 
>> ---
>> - Add missing Fixes tags.
>> - Fix memory ordering by emitting aq=1, rl=1
>>
>> Kuan-Wei Chiu (3):
>>    riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT
>>    riscv, bpf: Fix support for BPF_MOVSX in RV32 JIT
>>    riscv, bpf: Add 32 bit atomic operations to RV32 JIT
>>
>>   arch/riscv/net/bpf_jit_comp32.c | 101 +++++++++++++++++++++++++++-----
>>   1 file changed, 85 insertions(+), 16 deletions(-)
>>
>> -- 
>> 2.54.0.563.g4f69b47b94-goog
>>
> 
> _______________________________________________
> linux-riscv mailing list
> linux-riscv@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-riscv

  reply	other threads:[~2026-06-16  1:41 UTC|newest]

Thread overview: 11+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2026-05-11 22:16 Kuan-Wei Chiu
2026-05-11 22:16 ` [PATCH bpf-next v2 1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT Kuan-Wei Chiu
2026-06-17  6:53   ` Pu Lehui
2026-05-11 22:16 ` [PATCH bpf-next v2 2/3] riscv, bpf: Fix support for BPF_MOVSX " Kuan-Wei Chiu
2026-06-17  7:30   ` Pu Lehui
2026-06-22 21:28     ` Kuan-Wei Chiu
2026-05-11 22:16 ` [PATCH bpf-next v2 3/3] riscv, bpf: Add 32 bit atomic operations to " Kuan-Wei Chiu
2026-06-17  7:54   ` Pu Lehui
2026-06-15 16:18 ` [PATCH bpf-next v2 0/3] riscv, bpf: Fix signed operations and add 32 bit atomics Kuan-Wei Chiu
2026-06-16  1:41   ` Pu Lehui [this message]
2026-06-16  2:21     ` Kuan-Wei Chiu

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