From: Pu Lehui <pulehui@huawei.com>
To: Kuan-Wei Chiu <visitorckw@gmail.com>
Cc: <ast@kernel.org>, <daniel@iogearbox.net>, <andrii@kernel.org>,
<eddyz87@gmail.com>, <memxor@gmail.com>, <luke.r.nels@gmail.com>,
<xi.wang@gmail.com>, <pjw@kernel.org>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>, <martin.lau@linux.dev>,
<song@kernel.org>, <yonghong.song@linux.dev>, <jolsa@kernel.org>,
<alex@ghiti.fr>, <jserv@ccns.ncku.edu.tw>, <eleanor15x@gmail.com>,
<marscheng@google.com>, <bpf@vger.kernel.org>,
<linux-riscv@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH bpf-next v2 1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT
Date: Wed, 17 Jun 2026 14:53:16 +0800 [thread overview]
Message-ID: <c20a7c0e-121f-474c-945a-2a4705a45bd5@huawei.com> (raw)
In-Reply-To: <20260511221648.3251464-2-visitorckw@gmail.com>
lgtm, just some nits
On 2026/5/12 6:16, Kuan-Wei Chiu wrote:
> The current rv32 bpf jit compiler incorrectly treats BPF_SDIV and
> BPF_SMOD as unsigned operations. The BPF instruction set allows
> signed division and modulo by reusing the BPF_DIV and BPF_MOD opcodes
> with the instruction offset set to 1.
>
> Update the emit_alu_r32() function to accept an 'is_sdiv' variable and
> emit the correct div and rem instructions when the offset is 1.
>
> Before this patch:
> [ 44.161771] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times)
> [ 44.167385] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 ret 2147483645 != -3 (0x7ffffffd != 0xfffffffd)FAIL (1 times)
> [ 44.171053] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times)
> [ 44.172081] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 ret 1 != -1 (0x1 != 0xffffffff)FAIL (1 times)
>
> After this patch:
> [ 16.002192] test_bpf: #165 ALU_SDIV_X: -6 / 2 = -3 jited:1 95 PASS
> [ 16.002983] test_bpf: #166 ALU_SDIV_K: -6 / 2 = -3 jited:1 1059 PASS
> [ 16.017167] test_bpf: #169 ALU_SMOD_X: -7 % 2 = -1 jited:1 136 PASS
> [ 16.023002] test_bpf: #170 ALU_SMOD_K: -7 % 2 = -1 jited:1 109 PASS
>
> Fixes: ec0e2da95f72 ("bpf: Support new signed div/mod instructions.")
> Signed-off-by: Kuan-Wei Chiu <visitorckw@gmail.com>
> ---
> arch/riscv/net/bpf_jit_comp32.c | 19 ++++++++++++++-----
> 1 file changed, 14 insertions(+), 5 deletions(-)
>
> diff --git a/arch/riscv/net/bpf_jit_comp32.c b/arch/riscv/net/bpf_jit_comp32.c
> index 592dd86fbf81..7396899ea276 100644
> --- a/arch/riscv/net/bpf_jit_comp32.c
> +++ b/arch/riscv/net/bpf_jit_comp32.c
> @@ -509,7 +509,7 @@ static void emit_alu_r64(const s8 *dst, const s8 *src,
> }
>
> static void emit_alu_r32(const s8 *dst, const s8 *src,
> - struct rv_jit_context *ctx, const u8 op)
> + struct rv_jit_context *ctx, const u8 op, bool is_sdiv)
let's combind `op` and `is_sdiv` to `const struct bpf_insn *insn`, and
better to name `is_signed = insn->off == 1`
> {
> const s8 *tmp1 = bpf2rv32[TMP_REG_1];
> const s8 *tmp2 = bpf2rv32[TMP_REG_2];
> @@ -539,10 +539,16 @@ static void emit_alu_r32(const s8 *dst, const s8 *src,
> emit(rv_mul(lo(rd), lo(rd), lo(rs)), ctx);
> break;
> case BPF_DIV:
> - emit(rv_divu(lo(rd), lo(rd), lo(rs)), ctx);
> + if (is_sdiv)
> + emit(rv_div(lo(rd), lo(rd), lo(rs)), ctx);
> + else
> + emit(rv_divu(lo(rd), lo(rd), lo(rs)), ctx);
> break;
> case BPF_MOD:
> - emit(rv_remu(lo(rd), lo(rd), lo(rs)), ctx);
> + if (is_sdiv)
> + emit(rv_rem(lo(rd), lo(rd), lo(rs)), ctx);
> + else
> + emit(rv_remu(lo(rd), lo(rd), lo(rs)), ctx);
how about
emit(is_signed ? rv_rem(lo(rd) : rv_remu(lo(rd), lo(rd), lo(rs)), ctx)
> break;
> case BPF_LSH:
> emit(rv_sll(lo(rd), lo(rd), lo(rs)), ctx);
> @@ -959,6 +965,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> u8 code = insn->code;
> s16 off = insn->off;
> s32 imm = insn->imm;
> + bool is_sdiv = false;
>
> const s8 *dst = bpf2rv32[insn->dst_reg];
> const s8 *src = bpf2rv32[insn->src_reg];
> @@ -1041,7 +1048,9 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> emit_imm32(tmp2, imm, ctx);
> src = tmp2;
> }
> - emit_alu_r32(dst, src, ctx, BPF_OP(code));
> + if ((BPF_OP(code) == BPF_DIV || BPF_OP(code) == BPF_MOD) && insn->off == 1)
> + is_sdiv = true;
> + emit_alu_r32(dst, src, ctx, BPF_OP(code), is_sdiv);
> break;
>
> case BPF_ALU | BPF_MOV | BPF_K:
> @@ -1065,7 +1074,7 @@ int bpf_jit_emit_insn(const struct bpf_insn *insn, struct rv_jit_context *ctx,
> * src is ignored---choose tmp2 as a dummy register since it
> * is not on the stack.
> */
> - emit_alu_r32(dst, tmp2, ctx, BPF_OP(code));
> + emit_alu_r32(dst, tmp2, ctx, BPF_OP(code), false);
> break;
>
> case BPF_ALU | BPF_END | BPF_FROM_LE:
next prev parent reply other threads:[~2026-06-17 6:53 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-05-11 22:16 [PATCH bpf-next v2 0/3] riscv, bpf: Fix signed operations and add 32 bit atomics Kuan-Wei Chiu
2026-05-11 22:16 ` [PATCH bpf-next v2 1/3] riscv, bpf: Fix support for BPF_SDIV and BPF_SMOD in RV32 JIT Kuan-Wei Chiu
2026-06-17 6:53 ` Pu Lehui [this message]
2026-05-11 22:16 ` [PATCH bpf-next v2 2/3] riscv, bpf: Fix support for BPF_MOVSX " Kuan-Wei Chiu
2026-06-17 7:30 ` Pu Lehui
2026-06-22 21:28 ` Kuan-Wei Chiu
2026-05-11 22:16 ` [PATCH bpf-next v2 3/3] riscv, bpf: Add 32 bit atomic operations to " Kuan-Wei Chiu
2026-06-17 7:54 ` Pu Lehui
2026-06-15 16:18 ` [PATCH bpf-next v2 0/3] riscv, bpf: Fix signed operations and add 32 bit atomics Kuan-Wei Chiu
2026-06-16 1:41 ` Pu Lehui
2026-06-16 2:21 ` Kuan-Wei Chiu
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