* [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025)
@ 2025-10-04 22:25 Xose Vazquez Perez
2025-10-05 2:42 ` Borislav Petkov
0 siblings, 1 reply; 5+ messages in thread
From: Xose Vazquez Perez @ 2025-10-04 22:25 UTC (permalink / raw)
Cc: Xose Vazquez Perez, Thomas Gleixner, Ingo Molnar, H. Peter Anvin,
Peter Zijlstra, Josh Poimboeuf, Pawan Gupta, Nikolay Borisov,
Alex Murray, Andrew Cooper, Sohil Mehta, Greg Kroah-Hartman,
Borislav Petkov, Dave Hansen, X86-ML, KERNEL-ML
Update the minimum expected revisions of Intel microcode based on the
microcode-20250812 (Aug 2025) release:
https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250812
Since v6.18 will be released at the beginning of December 2025, this information
will be almost four months old by then.
μcode changelog:
Security updates rated HIGH:
INTEL-SA-01249
INTEL-SA-01308
INTEL-SA-01310
INTEL-SA-01311
INTEL-SA-01313
INTEL-SA-01367
Plus updates for functional issues for several CPUs.
CC: Thomas Gleixner <tglx@linutronix.de>
Cc: Ingo Molnar <mingo@redhat.com>
Cc: H. Peter Anvin <hpa@zytor.com>
Cc: Peter Zijlstra <peterz@infradead.org>
Cc: Josh Poimboeuf <jpoimboe@kernel.org>
Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
Cc: Nikolay Borisov <nik.borisov@suse.com>
Cc: Alex Murray <alex.murray@canonical.com>
Cc: Andrew Cooper <andrew.cooper3@citrix.com>
Cc: Sohil Mehta <sohil.mehta@intel.com>
Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
Cc: Borislav Petkov <bp@alien8.de>
Cc: Dave Hansen <dave.hansen@linux.intel.com>
Cc: Sohil Mehta <sohil.mehta@intel.com>
Cc: X86-ML <x86@kernel.org>
Cc: KERNEL-ML <linux-kernel@vger.kernel.org>
Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
---
.../kernel/cpu/microcode/intel-ucode-defs.h | 40 +++++++++----------
1 file changed, 20 insertions(+), 20 deletions(-)
diff --git a/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h b/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h
index 2d48e6593540..f5ed661a530c 100644
--- a/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h
+++ b/arch/x86/kernel/cpu/microcode/intel-ucode-defs.h
@@ -80,8 +80,8 @@
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x5f, .steppings = 0x0002, .driver_data = 0x3e },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x66, .steppings = 0x0008, .driver_data = 0x2a },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6a, .steppings = 0x0020, .driver_data = 0xc0002f0 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6a, .steppings = 0x0040, .driver_data = 0xd000404 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6c, .steppings = 0x0002, .driver_data = 0x10002d0 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6a, .steppings = 0x0040, .driver_data = 0xd000410 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x6c, .steppings = 0x0002, .driver_data = 0x10002e0 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7a, .steppings = 0x0002, .driver_data = 0x42 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7a, .steppings = 0x0100, .driver_data = 0x26 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x7e, .steppings = 0x0020, .driver_data = 0xca },
@@ -93,11 +93,11 @@
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x0400, .driver_data = 0xf6 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x0800, .driver_data = 0xf6 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8e, .steppings = 0x1000, .driver_data = 0x100 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0010, .driver_data = 0x2c0003f7 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0020, .driver_data = 0x2c0003f7 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0040, .driver_data = 0x2c0003f7 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0080, .driver_data = 0x2b000639 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0100, .driver_data = 0x2c0003f7 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0010, .driver_data = 0x2c000401 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0020, .driver_data = 0x2c000401 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0040, .driver_data = 0x2c000401 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0080, .driver_data = 0x2b000643 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x8f, .steppings = 0x0100, .driver_data = 0x2c000401 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x96, .steppings = 0x0002, .driver_data = 0x1a },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x97, .steppings = 0x0004, .driver_data = 0x3a },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0x97, .steppings = 0x0020, .driver_data = 0x3a },
@@ -115,27 +115,27 @@
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa6, .steppings = 0x0001, .driver_data = 0x102 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa6, .steppings = 0x0002, .driver_data = 0x100 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xa7, .steppings = 0x0002, .driver_data = 0x64 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaa, .steppings = 0x0010, .driver_data = 0x24 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xad, .steppings = 0x0002, .driver_data = 0xa0000d1 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaf, .steppings = 0x0008, .driver_data = 0x3000341 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaa, .steppings = 0x0010, .driver_data = 0x25 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xad, .steppings = 0x0002, .driver_data = 0xa000100 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xaf, .steppings = 0x0008, .driver_data = 0x3000362 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb5, .steppings = 0x0001, .driver_data = 0xa },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb7, .steppings = 0x0002, .driver_data = 0x12f },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xb7, .steppings = 0x0010, .driver_data = 0x12f },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0004, .driver_data = 0x4128 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0008, .driver_data = 0x4128 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0100, .driver_data = 0x4128 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbd, .steppings = 0x0002, .driver_data = 0x11f },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0004, .driver_data = 0x4129 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0008, .driver_data = 0x4129 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xba, .steppings = 0x0100, .driver_data = 0x4129 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbd, .steppings = 0x0002, .driver_data = 0x123 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbe, .steppings = 0x0001, .driver_data = 0x1d },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0004, .driver_data = 0x3a },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0020, .driver_data = 0x3a },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0040, .driver_data = 0x3a },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xbf, .steppings = 0x0080, .driver_data = 0x3a },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc5, .steppings = 0x0004, .driver_data = 0x118 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc6, .steppings = 0x0004, .driver_data = 0x118 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc6, .steppings = 0x0010, .driver_data = 0x118 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xca, .steppings = 0x0004, .driver_data = 0x118 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0002, .driver_data = 0x210002a9 },
-{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0004, .driver_data = 0x210002a9 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc5, .steppings = 0x0004, .driver_data = 0x119 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc6, .steppings = 0x0004, .driver_data = 0x119 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xc6, .steppings = 0x0010, .driver_data = 0x119 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xca, .steppings = 0x0004, .driver_data = 0x119 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0002, .driver_data = 0x210002b3 },
+{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0x6, .model = 0xcf, .steppings = 0x0004, .driver_data = 0x210002b3 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0xf, .model = 0x00, .steppings = 0x0080, .driver_data = 0x12 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0xf, .model = 0x00, .steppings = 0x0400, .driver_data = 0x15 },
{ .flags = X86_CPU_ID_FLAG_ENTRY_VALID, .vendor = X86_VENDOR_INTEL, .family = 0xf, .model = 0x01, .steppings = 0x0004, .driver_data = 0x2e },
--
2.51.0
^ permalink raw reply [flat|nested] 5+ messages in thread* Re: [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025)
2025-10-04 22:25 [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025) Xose Vazquez Perez
@ 2025-10-05 2:42 ` Borislav Petkov
2025-10-05 3:58 ` Dave Hansen
0 siblings, 1 reply; 5+ messages in thread
From: Borislav Petkov @ 2025-10-05 2:42 UTC (permalink / raw)
To: Xose Vazquez Perez
Cc: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra,
Josh Poimboeuf, Pawan Gupta, Nikolay Borisov, Alex Murray,
Andrew Cooper, Sohil Mehta, Greg Kroah-Hartman, Dave Hansen,
X86-ML, KERNEL-ML
On October 5, 2025 1:25:27 AM GMT+03:00, Xose Vazquez Perez <xose.vazquez@gmail.com> wrote:
>Update the minimum expected revisions of Intel microcode based on the
>microcode-20250812 (Aug 2025) release:
>https://github.com/intel/Intel-Linux-Processor-Microcode-Data-Files/releases/tag/microcode-20250812
>
>Since v6.18 will be released at the beginning of December 2025, this information
>will be almost four months old by then.
>
>
>μcode changelog:
> Security updates rated HIGH:
> INTEL-SA-01249
> INTEL-SA-01308
> INTEL-SA-01310
> INTEL-SA-01311
> INTEL-SA-01313
> INTEL-SA-01367
> Plus updates for functional issues for several CPUs.
>
>
>CC: Thomas Gleixner <tglx@linutronix.de>
>Cc: Ingo Molnar <mingo@redhat.com>
>Cc: H. Peter Anvin <hpa@zytor.com>
>Cc: Peter Zijlstra <peterz@infradead.org>
>Cc: Josh Poimboeuf <jpoimboe@kernel.org>
>Cc: Pawan Gupta <pawan.kumar.gupta@linux.intel.com>
>Cc: Nikolay Borisov <nik.borisov@suse.com>
>Cc: Alex Murray <alex.murray@canonical.com>
>Cc: Andrew Cooper <andrew.cooper3@citrix.com>
>Cc: Sohil Mehta <sohil.mehta@intel.com>
>Cc: Greg Kroah-Hartman <gregkh@linuxfoundation.org>
>Cc: Borislav Petkov <bp@alien8.de>
>Cc: Dave Hansen <dave.hansen@linux.intel.com>
>Cc: Sohil Mehta <sohil.mehta@intel.com>
>Cc: X86-ML <x86@kernel.org>
>Cc: KERNEL-ML <linux-kernel@vger.kernel.org>
>Signed-off-by: Xose Vazquez Perez <xose.vazquez@gmail.com>
>---
> .../kernel/cpu/microcode/intel-ucode-defs.h | 40 +++++++++----------
> 1 file changed, 20 insertions(+), 20 deletions(-)
This is turning into exactly what I was afraid and I warned it would turn onto:
1. https://git.kernel.org/tip/952df63ef426b21d6da14bb48748f12b0ae2fe36 - we *just* updated it and there's already a new one
2. Random people - not Intel - are going to be sending updates too.
This is a mess waiting to happen. ;-/
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025)
2025-10-05 2:42 ` Borislav Petkov
@ 2025-10-05 3:58 ` Dave Hansen
2025-10-05 5:27 ` Borislav Petkov
2025-10-05 14:35 ` Xose Vazquez Perez
0 siblings, 2 replies; 5+ messages in thread
From: Dave Hansen @ 2025-10-05 3:58 UTC (permalink / raw)
To: Borislav Petkov, Xose Vazquez Perez
Cc: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra,
Josh Poimboeuf, Pawan Gupta, Nikolay Borisov, Alex Murray,
Andrew Cooper, Sohil Mehta, Greg Kroah-Hartman, Dave Hansen,
X86-ML, KERNEL-ML
On 10/4/25 19:42, Borislav Petkov wrote:
> This is turning into exactly what I was afraid and I warned it would turn onto:
>
> 1. https://git.kernel.org/tip/952df63ef426b21d6da14bb48748f12b0ae2fe36 - we *just* updated it and there's already a new one
>
> 2. Random people - not Intel - are going to be sending updates too.
>
> This is a mess waiting to happen. ;-/
In the end, we've got an lightly documented patch that doesn't make a
lot of sense to apply. Not exactly a unique situation. ;)
Xose, do you have any specific, practical reasons this should be
applied? Honestly, I don't hold the "HIGH" Intel SA rating in super high
regard.
In short, why do you care?
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025)
2025-10-05 3:58 ` Dave Hansen
@ 2025-10-05 5:27 ` Borislav Petkov
2025-10-05 14:35 ` Xose Vazquez Perez
1 sibling, 0 replies; 5+ messages in thread
From: Borislav Petkov @ 2025-10-05 5:27 UTC (permalink / raw)
To: Dave Hansen, Xose Vazquez Perez
Cc: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra,
Josh Poimboeuf, Pawan Gupta, Nikolay Borisov, Alex Murray,
Andrew Cooper, Sohil Mehta, Greg Kroah-Hartman, Dave Hansen,
X86-ML, KERNEL-ML
On October 5, 2025 6:58:05 AM GMT+03:00, Dave Hansen <dave.hansen@intel.com> wrote:
>On 10/4/25 19:42, Borislav Petkov wrote:
>> This is turning into exactly what I was afraid and I warned it would turn onto:
>>
>> 1. https://git.kernel.org/tip/952df63ef426b21d6da14bb48748f12b0ae2fe36 - we *just* updated it and there's already a new one
>>
>> 2. Random people - not Intel - are going to be sending updates too.
>>
>> This is a mess waiting to happen. ;-/
>
>In the end, we've got an lightly documented patch that doesn't make a
>lot of sense to apply. Not exactly a unique situation. ;)
>
>Xose, do you have any specific, practical reasons this should be
>applied? Honestly, I don't hold the "HIGH" Intel SA rating in super high
>regard.
That's the problem. It'll be needless and endless discussions of the sort: oh, why do you need to update those revisions? But but, I need this and that. Oh but you don't. Blablabla... Upstream has these revisions, why aren't they backported...?
Versus: people should always update to the latest microcode and we're not tracking this in the kernel because there's really no need to.
And none of those issues exist anymore.
This is one of the reasons why I'm making sure the loader always works and is very easy to update microcode. You always update and that's it.
So you don't need any of that unnecessary work.
Thx.
Small device. Typos and formatting crap
^ permalink raw reply [flat|nested] 5+ messages in thread
* Re: [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025)
2025-10-05 3:58 ` Dave Hansen
2025-10-05 5:27 ` Borislav Petkov
@ 2025-10-05 14:35 ` Xose Vazquez Perez
1 sibling, 0 replies; 5+ messages in thread
From: Xose Vazquez Perez @ 2025-10-05 14:35 UTC (permalink / raw)
To: Dave Hansen, Borislav Petkov
Cc: Thomas Gleixner, Ingo Molnar, H. Peter Anvin, Peter Zijlstra,
Josh Poimboeuf, Pawan Gupta, Nikolay Borisov, Andrew Cooper,
Sohil Mehta, Greg Kroah-Hartman, Dave Hansen, X86-ML, KERNEL-ML
On 10/5/25 5:58 AM, Dave Hansen wrote:
> Xose, do you have any specific, practical reasons this should be
> applied? Honestly, I don't hold the "HIGH" Intel SA rating in super high
> regard.
> In short, why do you care?
It does not seem relevant that the kernel displays obsolete information.
It's that simple.
^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2025-10-05 14:35 UTC | newest]
Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed)
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2025-10-04 22:25 [PATCH RFC] x86/microcode/intel: Refresh the revisions that determine old_microcode to 20250812 (Aug 2025) Xose Vazquez Perez
2025-10-05 2:42 ` Borislav Petkov
2025-10-05 3:58 ` Dave Hansen
2025-10-05 5:27 ` Borislav Petkov
2025-10-05 14:35 ` Xose Vazquez Perez
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