Re: [PATCH] drm/rockchip: vop2: give rk3576 VP2 a primary plane

[Chaoyi Chen <chaoyi.chen@rock-chips.com>]

Hello Tomonori,

On 7/30/2026 7:24 AM, Tomonori Nakagawa wrote:
> The rk3576 VOP2 has three video ports. VP0 and VP1 each have a Cluster
> window that acts as their primary plane, but VP2 - the port wired to the
> DesignWare DP controller - only has Esmart windows, all typed
> DRM_PLANE_TYPE_OVERLAY.

The description here is not accurate. VP2 can wire to different
display interfaces which depending on your board configuration.

> 
> The driver requires every active video port to own a
> DRM_PLANE_TYPE_PRIMARY plane. When VP2 is driven (a board that uses the
> DP output) it finds none, CRTC creation returns -ENOENT, and the whole
> VOP2 bind fails, taking down the entire display subsystem.
> 
> Promote Esmart0 to DRM_PLANE_TYPE_PRIMARY so VP2 has a primary plane.
> Esmart0's possible_vp_mask already includes VP2 (BIT(2)) and its
> layer_sel_id[2] = 0 is a valid VP2 layer slot, while VP0 keeps Cluster0
> as its primary, so the existing VP0/VP1 assignments are unchanged:
> 
>   VP0: primary=Cluster0, overlay=Esmart2
>   VP1: primary=Cluster1, overlays=Esmart1, Esmart3
>   VP2: primary=Esmart0,  overlays=Esmart1, Esmart2, Esmart3
> 
> Tested on Anbernic RG Vita Pro (rk3576) with the DP alt-mode output.
> 
> Signed-off-by: Tomonori Nakagawa <jack@supremeoverlordjabs.co>
> ---
>  drivers/gpu/drm/rockchip/rockchip_vop2_reg.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> index 17eda592b..e7d013dc3 100644
> --- a/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> +++ b/drivers/gpu/drm/rockchip/rockchip_vop2_reg.c
> @@ -894,7 +894,7 @@ static const struct vop2_win_data rk3576_vop_win_data[] = {
>  		.format_modifiers = format_modifiers,
>  		.layer_sel_id = { 2, 0xf, 0, 0xf },
>  		.supported_rotations = DRM_MODE_REFLECT_Y,
> -		.type = DRM_PLANE_TYPE_OVERLAY,
> +		.type = DRM_PLANE_TYPE_PRIMARY,
>  		.axi_bus_id = 0,
>  		.axi_yrgb_r_id = 0x10,
>  		.axi_uv_r_id = 0x11,

-- 
Best, 
Chaoyi