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From: "Liao, Chang" <liaochang1@huawei.com>
To: <kristina.martsenko@arm.com>, <catalin.marinas@arm.com>,
	<will@kernel.org>, <mark.rutland@arm.com>, <sashal@kernel.org>,
	<yangjiangshui@h-partners.com>, <zouyipeng@huawei.com>,
	<justin.he@arm.com>, <zengheng4@huawei.com>,
	<yangyicong@hisilicon.com>, ruanjinjie <ruanjinjie@huawei.com>
Cc: <inux-arm-kernel@lists.infradead.org>, <linux-kernel@vger.kernel.org>
Subject: [RFC] SCTLR_EL1.TIDCP toggling for performance
Date: Fri, 18 Jul 2025 10:32:00 +0800	[thread overview]
Message-ID: <24afb8de-622a-4865-bd8e-8e89ccfff8f4@huawei.com> (raw)

Hi, Kristina

I've reviewed your patch [1] for FEAT_TIDCP1 support, which by default traps EL0
accesses to implementation-defined system registers and instructions at EL1/EL2.

Do you have any plans to add support for toggling the SCTLR_EL1.TIDCP1 bit? I'm
encountering performance degradation on CPU where certain implementation-defined
registers and instructions are designed for EL0 performance use. The trapping
overhead is substantial enough to compromise any benefits, and it's even worse
in virtualization. Therefore, I'm hoping there's a way to clear the SCTLR_EL1.TIDCP1
bit on such platforms, perhaps via a kernel config option or command-line parameter.
Alternatively, do you have a better solution for gracefully toggling this bit on
and off?

Thanks

[1] https://lore.kernel.org/linux-arm-kernel/Yrw3NWkH6D0CgRsF@sirena.org.uk/T/#m5cfdb27b48d9d7e30db73e991fc6c232ba8a7349

-- 
BR
Liao, Chang


             reply	other threads:[~2025-07-18  2:32 UTC|newest]

Thread overview: 5+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-07-18  2:32 Liao, Chang [this message]
2025-07-18 17:28 ` Kristina Martšenko
2025-07-22  1:47   ` Liao, Chang
2025-07-18 19:03 ` Catalin Marinas
2025-07-22  1:47   ` Liao, Chang

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