Re: [PATCH 3/4] arm64: dts: socfpga: agilex5: enable gmac2 on the Agilex5 dev kit

[Matthew Gerlach <matthew.gerlach@altera.com>]

On 7/14/25 10:25 AM, Andrew Lunn wrote:
> > +&gmac2 {
> > +	status = "okay";
> > +	phy-mode = "rgmii";	/* Delays implemented by the IO ring of the Agilex5 SOCFPGA. */
>
> Please could you explain in more details what this means.
>
> The normal meaning for 'rgmii' is that the PCB implements the delay. I
> just want to fully understand what this IO ring is, and if it is part
> of the PCB.

The IO ring is the logic in the Agilex5 that controls the pins on the 
chip. It is this logic that sits between the MAC IP in the Agilex5 and 
the pins connected to the PCB that is inserting the necessary delays. 
Technically the PCB is not implementing the delays, but the "wires" 
between the MAC and the external pins of the Agilex5 are implementing 
the delay. It seems to me that "rgmii" is a more accurate description of 
the hardware than "rgmii-id" in this case.

>
> > +	phy-handle = <&emac2_phy0>;
> > +	max-frame-size = <9000>;
> > +	mdio0 {
> > +		#address-cells = <1>;
> > +		#size-cells = <0>;
> > +		compatible = "snps,dwmac-mdio";
> > +		emac2_phy0: ethernet-phy@0 {
> > +			reg = <0>;
> > +		};
>
> Please add a newline in here to separate the inner node from the
> rest.
>
>      Andrew

I will add a newline before the emac2_phy0 node as suggested in v2.

Thanks for the feedback,
Matthew Gerlach
>
> ---
> pw-bot: cr