Re: [PATCH v1] PCI: endpoint: Skip upper halves of 64-bit BARs during search

[Manikanta Maddireddy <mmaddireddy@nvidia.com>]

On 21/10/26 7:55 pm, Niklas Cassel wrote:
> On Wed, Oct 21, 2026 at 12:46:03PM +0200, Niklas Cassel wrote:
>> On Wed, Oct 21, 2026 at 01:36:44PM +0530, Manikanta Maddireddy wrote:
>>> pci_epc_get_next_free_bar() skips the upper half of a 64-bit BAR only
>>> when it is the starting BAR. If the search subsequently passes a
>>> reserved or disabled 64-bit BAR, it can return its upper half as an
>>> independent BAR because that slot has a default programmable descriptor.
>>>
>>> For example, Tegra exposes a programmable 64-bit BAR0 and reserved
>>> 64-bit BAR2 and BAR4. A search starting at BAR1 skips BAR1 and BAR2,
>>> then incorrectly returns BAR3. The next search can similarly return
>>> BAR5, causing the EPF test driver to allocate and program BARs that
>>> belong to the reserved hardware windows.
>>
> 
>> 12a22fb38cbb ("PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as
>> 64-bit BAR_RESERVED").
>>
>>
>> I'm fine with this patch, but I think you need to rephrase the kdoc
>> to reflect this new reality, because currently the kdoc is confusing/
>> not in line with the 'new' meaning of BAR_RESERVED, which can contain
>> MSI-X table etc.
> 
> To clarify, I can see that you updated the definition in:
> 27ce1d8ecb9b ("PCI: endpoint: Allow only_64bit on BAR_RESERVED")
> 
> 
> But, IMO it is still not super clear.
> 
> Perhaps we should have mentioned explicitly that only_64bit is
> also allowed on a BAR_RESERVED, if that reserved BAR is 64-bit.
> (Since that use case is different from what the kdoc currently
> says.)
> 
> 
> I also think that this patch needs a Fixes tag with either:
> 27ce1d8ecb9b ("PCI: endpoint: Allow only_64bit on BAR_RESERVED")
> or
> 12a22fb38cbb ("PCI: tegra194: Expose BAR2 (MSI-X) and BAR4 (DMA) as
> 64-bit BAR_RESERVED")
> 
> 
> Kind regards,
> Niklas

Hi,

I will send V2 with kdoc update and Fixes tag.

- Manikanta

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