* [PATCH 1/1] dmaengine: xilinx: xdma: Add regmap register ranges
@ 2025-10-14 5:50 Alexander Stein
2025-10-14 17:19 ` Lizhi Hou
0 siblings, 1 reply; 2+ messages in thread
From: Alexander Stein @ 2025-10-14 5:50 UTC (permalink / raw)
To: Lizhi Hou, Brian Xu, Raj Kumar Rampelli, Vinod Koul, Michal Simek
Cc: Alexander Stein, dmaengine, linux-arm-kernel, linux-kernel
The XDMA bar is 64KiB, way too much for debugfs dump. Add register range
definitions for all defined registers in PG195. As this is PCIe memory
range all readable registers are marked as volatile.
Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
---
Although the change itself is independent, this patch context depends on
[1].
[1] https://lore.kernel.org/all/20251013-xdma-max-reg-v5-1-83efeedce19d@amarulasolutions.com/
drivers/dma/xilinx/xdma.c | 89 +++++++++++++++++++++++++++++++++++++++
1 file changed, 89 insertions(+)
diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c
index 5ecf8223c112e..3d9e92bbc9bb0 100644
--- a/drivers/dma/xilinx/xdma.c
+++ b/drivers/dma/xilinx/xdma.c
@@ -33,12 +33,101 @@
#include "../virt-dma.h"
#include "xdma-regs.h"
+static const struct regmap_range xdma_wr_ranges[] = {
+ /* H2C channel registers */
+ regmap_reg_range(0x0004, 0x000c),
+ regmap_reg_range(0x0040, 0x0040),
+ regmap_reg_range(0x0088, 0x0098),
+ regmap_reg_range(0x00c0, 0x00c0),
+ /* C2H channel registers */
+ regmap_reg_range(0x1004, 0x100c),
+ regmap_reg_range(0x1040, 0x1040),
+ regmap_reg_range(0x1088, 0x1098),
+ regmap_reg_range(0x10c0, 0x10c0),
+ /* IRQ Block registers */
+ regmap_reg_range(0x2004, 0x2018),
+ regmap_reg_range(0x2080, 0x208c),
+ regmap_reg_range(0x20a0, 0x20a4),
+ /* Config Block registers */
+ regmap_reg_range(0x301c, 0x301c),
+ regmap_reg_range(0x3040, 0x3044),
+ regmap_reg_range(0x3060, 0x3060),
+ /* H2C SGDMA registers */
+ regmap_reg_range(0x4080, 0x408c),
+ /* C2H SGDMA registers */
+ regmap_reg_range(0x5080, 0x508c),
+ /* SGDMA Common registers */
+ regmap_reg_range(0x6010, 0x6018),
+ regmap_reg_range(0x6020, 0x6028),
+ /* MSI-X Vector Table and PBA */
+ regmap_reg_range(0x8000, 0x81fc),
+ regmap_reg_range(0x8fe0, 0x8fe0),
+};
+static const struct regmap_range xdma_rd_ranges[] = {
+ /* H2C channel registers */
+ regmap_reg_range(0x0000, 0x0004),
+ regmap_reg_range(0x0040, 0x004c),
+ regmap_reg_range(0x0088, 0x0090),
+ regmap_reg_range(0x00c0, 0x00d0),
+ /* C2H channel registers */
+ regmap_reg_range(0x1000, 0x1004),
+ regmap_reg_range(0x1040, 0x104c),
+ regmap_reg_range(0x1088, 0x1090),
+ regmap_reg_range(0x10c0, 0x10d0),
+ /* IRQ Block registers */
+ regmap_reg_range(0x2000, 0x2004),
+ regmap_reg_range(0x2010, 0x2010),
+ regmap_reg_range(0x2040, 0x204c),
+ regmap_reg_range(0x2080, 0x208c),
+ regmap_reg_range(0x20a0, 0x20a4),
+ /* Config Block registers */
+ regmap_reg_range(0x3000, 0x301c),
+ regmap_reg_range(0x3040, 0x3044),
+ regmap_reg_range(0x3060, 0x3060),
+ /* H2C SGDMA registers */
+ regmap_reg_range(0x4000, 0x4000),
+ regmap_reg_range(0x4080, 0x408c),
+ /* C2H SGDMA registers */
+ regmap_reg_range(0x5000, 0x5000),
+ regmap_reg_range(0x5080, 0x508c),
+ /* SGDMA Common registers */
+ regmap_reg_range(0x6000, 0x6000),
+ regmap_reg_range(0x6010, 0x6010),
+ regmap_reg_range(0x6020, 0x6020),
+ /* MSI-X Vector Table and PBA */
+ regmap_reg_range(0x8000, 0x81fc),
+ regmap_reg_range(0x8fe0, 0x8fe0),
+};
+static const struct regmap_range xdma_precious_ranges[] = {
+ /* H2C channel registers */
+ regmap_reg_range(0x0044, 0x0044),
+ /* C2H channel registers */
+ regmap_reg_range(0x1044, 0x1044),
+};
+static const struct regmap_access_table xdma_wr_table = {
+ .yes_ranges = xdma_wr_ranges,
+ .n_yes_ranges = ARRAY_SIZE(xdma_wr_ranges),
+};
+static const struct regmap_access_table xdma_rd_table = {
+ .yes_ranges = xdma_rd_ranges,
+ .n_yes_ranges = ARRAY_SIZE(xdma_rd_ranges),
+};
+static const struct regmap_access_table xdma_precious_table = {
+ .yes_ranges = xdma_precious_ranges,
+ .n_yes_ranges = ARRAY_SIZE(xdma_precious_ranges),
+};
+
/* mmio regmap config for all XDMA registers */
static const struct regmap_config xdma_regmap_config = {
.reg_bits = 32,
.val_bits = 32,
.reg_stride = 4,
.max_register = XDMA_MAX_REG_OFFSET,
+ .wr_table = &xdma_wr_table,
+ .rd_table = &xdma_rd_table,
+ .volatile_table = &xdma_rd_table,
+ .precious_table = &xdma_precious_table,
+ .cache_type = REGCACHE_NONE,
};
/**
--
2.43.0
^ permalink raw reply [flat|nested] 2+ messages in thread
* Re: [PATCH 1/1] dmaengine: xilinx: xdma: Add regmap register ranges
2025-10-14 5:50 [PATCH 1/1] dmaengine: xilinx: xdma: Add regmap register ranges Alexander Stein
@ 2025-10-14 17:19 ` Lizhi Hou
0 siblings, 0 replies; 2+ messages in thread
From: Lizhi Hou @ 2025-10-14 17:19 UTC (permalink / raw)
To: Alexander Stein, Brian Xu, Raj Kumar Rampelli, Vinod Koul, Michal Simek
Cc: dmaengine, linux-arm-kernel, linux-kernel
Reviewed-by: Lizhi Hou <lizhi.hou@amd.com>
On 10/13/25 22:50, Alexander Stein wrote:
> The XDMA bar is 64KiB, way too much for debugfs dump. Add register range
> definitions for all defined registers in PG195. As this is PCIe memory
> range all readable registers are marked as volatile.
>
> Signed-off-by: Alexander Stein <alexander.stein@ew.tq-group.com>
> ---
> Although the change itself is independent, this patch context depends on
> [1].
>
> [1] https://lore.kernel.org/all/20251013-xdma-max-reg-v5-1-83efeedce19d@amarulasolutions.com/
>
> drivers/dma/xilinx/xdma.c | 89 +++++++++++++++++++++++++++++++++++++++
> 1 file changed, 89 insertions(+)
>
> diff --git a/drivers/dma/xilinx/xdma.c b/drivers/dma/xilinx/xdma.c
> index 5ecf8223c112e..3d9e92bbc9bb0 100644
> --- a/drivers/dma/xilinx/xdma.c
> +++ b/drivers/dma/xilinx/xdma.c
> @@ -33,12 +33,101 @@
> #include "../virt-dma.h"
> #include "xdma-regs.h"
>
> +static const struct regmap_range xdma_wr_ranges[] = {
> + /* H2C channel registers */
> + regmap_reg_range(0x0004, 0x000c),
> + regmap_reg_range(0x0040, 0x0040),
> + regmap_reg_range(0x0088, 0x0098),
> + regmap_reg_range(0x00c0, 0x00c0),
> + /* C2H channel registers */
> + regmap_reg_range(0x1004, 0x100c),
> + regmap_reg_range(0x1040, 0x1040),
> + regmap_reg_range(0x1088, 0x1098),
> + regmap_reg_range(0x10c0, 0x10c0),
> + /* IRQ Block registers */
> + regmap_reg_range(0x2004, 0x2018),
> + regmap_reg_range(0x2080, 0x208c),
> + regmap_reg_range(0x20a0, 0x20a4),
> + /* Config Block registers */
> + regmap_reg_range(0x301c, 0x301c),
> + regmap_reg_range(0x3040, 0x3044),
> + regmap_reg_range(0x3060, 0x3060),
> + /* H2C SGDMA registers */
> + regmap_reg_range(0x4080, 0x408c),
> + /* C2H SGDMA registers */
> + regmap_reg_range(0x5080, 0x508c),
> + /* SGDMA Common registers */
> + regmap_reg_range(0x6010, 0x6018),
> + regmap_reg_range(0x6020, 0x6028),
> + /* MSI-X Vector Table and PBA */
> + regmap_reg_range(0x8000, 0x81fc),
> + regmap_reg_range(0x8fe0, 0x8fe0),
> +};
> +static const struct regmap_range xdma_rd_ranges[] = {
> + /* H2C channel registers */
> + regmap_reg_range(0x0000, 0x0004),
> + regmap_reg_range(0x0040, 0x004c),
> + regmap_reg_range(0x0088, 0x0090),
> + regmap_reg_range(0x00c0, 0x00d0),
> + /* C2H channel registers */
> + regmap_reg_range(0x1000, 0x1004),
> + regmap_reg_range(0x1040, 0x104c),
> + regmap_reg_range(0x1088, 0x1090),
> + regmap_reg_range(0x10c0, 0x10d0),
> + /* IRQ Block registers */
> + regmap_reg_range(0x2000, 0x2004),
> + regmap_reg_range(0x2010, 0x2010),
> + regmap_reg_range(0x2040, 0x204c),
> + regmap_reg_range(0x2080, 0x208c),
> + regmap_reg_range(0x20a0, 0x20a4),
> + /* Config Block registers */
> + regmap_reg_range(0x3000, 0x301c),
> + regmap_reg_range(0x3040, 0x3044),
> + regmap_reg_range(0x3060, 0x3060),
> + /* H2C SGDMA registers */
> + regmap_reg_range(0x4000, 0x4000),
> + regmap_reg_range(0x4080, 0x408c),
> + /* C2H SGDMA registers */
> + regmap_reg_range(0x5000, 0x5000),
> + regmap_reg_range(0x5080, 0x508c),
> + /* SGDMA Common registers */
> + regmap_reg_range(0x6000, 0x6000),
> + regmap_reg_range(0x6010, 0x6010),
> + regmap_reg_range(0x6020, 0x6020),
> + /* MSI-X Vector Table and PBA */
> + regmap_reg_range(0x8000, 0x81fc),
> + regmap_reg_range(0x8fe0, 0x8fe0),
> +};
> +static const struct regmap_range xdma_precious_ranges[] = {
> + /* H2C channel registers */
> + regmap_reg_range(0x0044, 0x0044),
> + /* C2H channel registers */
> + regmap_reg_range(0x1044, 0x1044),
> +};
> +static const struct regmap_access_table xdma_wr_table = {
> + .yes_ranges = xdma_wr_ranges,
> + .n_yes_ranges = ARRAY_SIZE(xdma_wr_ranges),
> +};
> +static const struct regmap_access_table xdma_rd_table = {
> + .yes_ranges = xdma_rd_ranges,
> + .n_yes_ranges = ARRAY_SIZE(xdma_rd_ranges),
> +};
> +static const struct regmap_access_table xdma_precious_table = {
> + .yes_ranges = xdma_precious_ranges,
> + .n_yes_ranges = ARRAY_SIZE(xdma_precious_ranges),
> +};
> +
> /* mmio regmap config for all XDMA registers */
> static const struct regmap_config xdma_regmap_config = {
> .reg_bits = 32,
> .val_bits = 32,
> .reg_stride = 4,
> .max_register = XDMA_MAX_REG_OFFSET,
> + .wr_table = &xdma_wr_table,
> + .rd_table = &xdma_rd_table,
> + .volatile_table = &xdma_rd_table,
> + .precious_table = &xdma_precious_table,
> + .cache_type = REGCACHE_NONE,
> };
>
> /**
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