From: Jessica Zhang <quic_jesszhan@quicinc.com>
To: Dmitry Baryshkov <dmitry.baryshkov@linaro.org>
Cc: <freedreno@lists.freedesktop.org>,
David Airlie <airlied@gmail.com>, <quic_abhinavk@quicinc.com>,
<dri-devel@lists.freedesktop.org>, <linux-kernel@vger.kernel.org>,
Rob Clark <robdclark@gmail.com>,
"Daniel Vetter" <daniel@ffwll.ch>,
<linux-arm-msm@vger.kernel.org>,
Marijn Suijten <marijn.suijten@somainline.org>,
Sean Paul <sean@poorly.run>
Subject: Re: [Freedreno] [PATCH 0/2] drm/msm/dpu: INTF CRC configuration cleanups and fix
Date: Tue, 12 Dec 2023 18:37:08 -0800 [thread overview]
Message-ID: <27423c14-bdcb-4053-a7c3-b2c9d6c4e771@quicinc.com> (raw)
In-Reply-To: <CAA8EJpof5LO7pyXaqgtbL=sL2a2Te2tzLF-NrTFT7n58pB3iww@mail.gmail.com>
On 11/30/2023 11:39 PM, Dmitry Baryshkov wrote:
> On Fri, 1 Dec 2023 at 03:31, Jessica Zhang <quic_jesszhan@quicinc.com> wrote:
>>
>> This series drops the frame_count and enable parameters (as they're always
>> set to the same value). It also sets input_sel=0x1 for INTF.
>>
>> Signed-off-by: Jessica Zhang <quic_jesszhan@quicinc.com>
>> ---
>> Jessica Zhang (2):
>> drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr()
>> drm/msm/dpu: Set input_sel bit for INTF
>
> Please change the order of the commits: fix (input_sel) comes first,
> then comes the improvement.
> Otherwise if one needs to backport this fix, they either need to pick
> up the irrelevant patch, or they have to rework the fix.
Acked.
Thanks,
Jessica Zhang
>
>>
>> drivers/gpu/drm/msm/disp/dpu1/dpu_crtc.c | 4 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_encoder.c | 4 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.c | 6 +++---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_intf.h | 4 ++--
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.c | 6 +++---
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_lm.h | 3 ++-
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.c | 18 +++++++-----------
>> drivers/gpu/drm/msm/disp/dpu1/dpu_hw_util.h | 11 +++++------
>> 8 files changed, 26 insertions(+), 30 deletions(-)
>> ---
>> base-commit: 4047f50eb64d980fcd581a19bbe6164dab25ebc7
>> change-id: 20231122-encoder-fixup-61c190b16085
>>
>> Best regards,
>> --
>> Jessica Zhang <quic_jesszhan@quicinc.com>
>>
>
>
> --
> With best wishes
> Dmitry
prev parent reply other threads:[~2023-12-13 2:37 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-12-01 1:30 Jessica Zhang
2023-12-01 1:30 ` [PATCH 1/2] drm/msm/dpu: Drop enable and frame_count parameters from dpu_hw_setup_misr() Jessica Zhang
2023-12-01 7:38 ` Dmitry Baryshkov
2023-12-01 1:30 ` [PATCH 2/2] drm/msm/dpu: Set input_sel bit for INTF Jessica Zhang
2023-12-01 7:36 ` Dmitry Baryshkov
2023-12-01 21:29 ` Abhinav Kumar
2023-12-02 19:54 ` Dmitry Baryshkov
2023-12-13 19:51 ` Jessica Zhang
2023-12-01 7:39 ` [PATCH 0/2] drm/msm/dpu: INTF CRC configuration cleanups and fix Dmitry Baryshkov
2023-12-13 2:37 ` Jessica Zhang [this message]
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