From: <Ryan.Wanner@microchip.com>
To: <lee@kernel.org>, <robh@kernel.org>, <krzk+dt@kernel.org>,
<conor+dt@kernel.org>, <claudiu.beznea@tuxon.dev>,
<sre@kernel.org>, <nicolas.ferre@microchip.com>,
<alexandre.belloni@bootlin.com>, <p.zabel@pengutronix.de>
Cc: <linux@armlinux.org.uk>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <linux-pm@vger.kernel.org>,
<linux-arm-kernel@lists.infradead.org>,
<linux-rtc@vger.kernel.org>, Li Bin <bin.li@microchip.com>,
Ryan Wanner <Ryan.Wanner@microchip.com>,
"Durai Manickam KR" <durai.manickamkr@microchip.com>,
Andrei Simion <andrei.simion@microchip.com>
Subject: [PATCH v3 09/21] ARM: at91: pm: fix at91_suspend_finish for ZQ calibration
Date: Thu, 27 Feb 2025 08:51:56 -0700 [thread overview]
Message-ID: <28b33f9bcd0ca60ceba032969fe054d38f2b9577.1740671156.git.Ryan.Wanner@microchip.com> (raw)
In-Reply-To: <cover.1740671156.git.Ryan.Wanner@microchip.com>
From: Li Bin <bin.li@microchip.com>
For sama7g5 and sama7d65 backup mode, we encountered a "ZQ calibrate error"
during recalibrating the impedance in BootStrap.
We found that the impedance value saved in at91_suspend_finish() before
the DDR entered self-refresh mode did not match the resistor values. The
ZDATA field in the DDR3PHY_ZQ0CR0 register uses a modified gray code to
select the different impedance setting.
But these gray code are incorrect, a workaournd from design team fixed the
bug in the calibration logic. The ZDATA contains four independent impedance
elements, but the algorithm combined the four elements into one. The elements
were fixed using properly shifted offsets.
Signed-off-by: Li Bin <bin.li@microchip.com>
[nicolas.ferre@microchip.com: fix indentation and combine 2 patches]
Signed-off-by: Nicolas Ferre <nicolas.ferre@microchip.com>
Tested-by: Ryan Wanner <Ryan.Wanner@microchip.com>
Tested-by: Durai Manickam KR <durai.manickamkr@microchip.com>
Tested-by: Andrei Simion <andrei.simion@microchip.com>
Signed-off-by: Ryan Wanner <Ryan.Wanner@microchip.com>
---
arch/arm/mach-at91/pm.c | 21 +++++++++++----------
1 file changed, 11 insertions(+), 10 deletions(-)
diff --git a/arch/arm/mach-at91/pm.c b/arch/arm/mach-at91/pm.c
index 05a1547642b6..6c3e6aa22606 100644
--- a/arch/arm/mach-at91/pm.c
+++ b/arch/arm/mach-at91/pm.c
@@ -545,11 +545,12 @@ extern u32 at91_pm_suspend_in_sram_sz;
static int at91_suspend_finish(unsigned long val)
{
- unsigned char modified_gray_code[] = {
- 0x00, 0x01, 0x02, 0x03, 0x06, 0x07, 0x04, 0x05, 0x0c, 0x0d,
- 0x0e, 0x0f, 0x0a, 0x0b, 0x08, 0x09, 0x18, 0x19, 0x1a, 0x1b,
- 0x1e, 0x1f, 0x1c, 0x1d, 0x14, 0x15, 0x16, 0x17, 0x12, 0x13,
- 0x10, 0x11,
+ /* SYNOPSYS workaround to fix a bug in the calibration logic */
+ unsigned char modified_fix_code[] = {
+ 0x00, 0x01, 0x01, 0x06, 0x07, 0x0c, 0x06, 0x07, 0x0b, 0x18,
+ 0x0a, 0x0b, 0x0c, 0x0d, 0x0d, 0x0a, 0x13, 0x13, 0x12, 0x13,
+ 0x14, 0x15, 0x15, 0x12, 0x18, 0x19, 0x19, 0x1e, 0x1f, 0x14,
+ 0x1e, 0x1f,
};
unsigned int tmp, index;
int i;
@@ -560,25 +561,25 @@ static int at91_suspend_finish(unsigned long val)
* restore the ZQ0SR0 with the value saved here. But the
* calibration is buggy and restoring some values from ZQ0SR0
* is forbidden and risky thus we need to provide processed
- * values for these (modified gray code values).
+ * values for these.
*/
tmp = readl(soc_pm.data.ramc_phy + DDR3PHY_ZQ0SR0);
/* Store pull-down output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDO_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] = modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] = modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDO_OFF;
/* Store pull-up output impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PUO_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PUO_OFF;
/* Store pull-down on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SR0_PDODT_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SR0_PDODT_OFF;
/* Store pull-up on-die termination impedance select. */
index = (tmp >> DDR3PHY_ZQ0SRO_PUODT_OFF) & 0x1f;
- soc_pm.bu->ddr_phy_calibration[0] |= modified_gray_code[index];
+ soc_pm.bu->ddr_phy_calibration[0] |= modified_fix_code[index] << DDR3PHY_ZQ0SRO_PUODT_OFF;
/*
* The 1st 8 words of memory might get corrupted in the process
--
2.43.0
next prev parent reply other threads:[~2025-02-27 15:53 UTC|newest]
Thread overview: 39+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-02-27 15:51 [PATCH v3 00/21] Enable Power Modes Support for SAMA7D65 SoC Ryan.Wanner
2025-02-27 15:51 ` [PATCH v3 01/21] dt-bindings: mfd: syscon: add microchip,sama7d65-ddr3phy Ryan.Wanner
2025-03-21 11:32 ` (subset) " Lee Jones
2025-02-27 15:51 ` [PATCH v3 02/21] dt-bindings: mfd: syscon: add microchip,sama7d65-sfrbu Ryan.Wanner
2025-02-28 21:22 ` Rob Herring (Arm)
2025-03-21 11:32 ` (subset) " Lee Jones
2025-02-27 15:51 ` [PATCH v3 03/21] dt-bindings: sram: Add microchip,sama7d65-sram Ryan.Wanner
2025-02-27 15:51 ` [PATCH v3 04/21] dt-bindings: power: reset: atmel,sama5d2-shdwc: Add microchip,sama7d65-shdwc Ryan.Wanner
2025-02-27 15:51 ` [PATCH v3 05/21] dt-bindings: reset: atmel,at91sam9260-reset: add microchip,sama7d65-rstc Ryan.Wanner
2025-02-27 15:51 ` [PATCH v3 06/21] dt-bindings: rtc: at91rm9200: add microchip,sama7d65-rtc Ryan.Wanner
2025-02-28 21:22 ` Rob Herring (Arm)
2025-02-27 15:51 ` [PATCH v3 07/21] dt-bindings: at91rm9260-rtt: add microchip,sama7d65-rtt Ryan.Wanner
2025-02-28 21:23 ` Rob Herring (Arm)
2025-02-27 15:51 ` [PATCH v3 08/21] ARM: at91: Add PM support to sama7d65 Ryan.Wanner
2025-03-03 8:26 ` Claudiu Beznea
2025-02-27 15:51 ` Ryan.Wanner [this message]
2025-02-27 15:51 ` [PATCH v3 10/21] ARM: at91: pm: add DT compatible support for sama7d65 Ryan.Wanner
2025-03-03 8:37 ` claudiu beznea (tuxon)
2025-02-27 15:51 ` [PATCH v3 11/21] ARM: at91: PM: Add Backup mode for SAMA7D65 Ryan.Wanner
2025-03-03 8:37 ` claudiu beznea (tuxon)
2025-02-27 15:51 ` [PATCH v3 12/21] ARM: at91: pm: Enable ULP0/ULP1 " Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 13/21] power: reset: at91-sama5d2_shdwc: Add sama7d65 PMC Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 14/21] ARM: dts: microchip: sama7d65: Add SRAM and DRAM components support Ryan.Wanner
2025-03-03 8:28 ` Claudiu Beznea
2025-02-27 15:52 ` [PATCH v3 15/21] ARM: dts: microchip: sama7d65: Add Reset Controller to sama7d65 SoC Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 16/21] ARM: dts: microchip: sama7d65: Add Shutdown controller support Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 17/21] ARM: dts: microchip: sama7d65: Add RTT and GPBR Support for sama7d65 SoC Ryan.Wanner
2025-03-03 8:28 ` Claudiu Beznea
2025-03-03 8:38 ` claudiu beznea (tuxon)
2025-02-27 15:52 ` [PATCH v3 18/21] ARM: dts: microchip: sama7d65: Add RTC support for sama7d65 Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 19/21] ARM: dts: microchip: sama7d65: Add SFRBU support to sama7d65 Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 20/21] ARM: dts: microchip: sama7d65: Enable shutdown controller Ryan.Wanner
2025-02-27 15:52 ` [PATCH v3 21/21] ARM: dts: microchip: sama7d65: Add RTT timer to curiosity board Ryan.Wanner
2025-02-28 14:23 ` [PATCH v3 00/21] Enable Power Modes Support for SAMA7D65 SoC Rob Herring (Arm)
2025-03-03 8:40 ` Claudiu Beznea
2025-03-05 17:39 ` Ryan Wanner
2025-03-08 0:38 ` (subset) " Sebastian Reichel
2025-03-13 16:42 ` Lee Jones
2025-03-17 19:29 ` Ryan.Wanner
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