[PATCH] mmc: dw_mmc-pltfm: Fix usage of phase_map for SoCFPGA

[PATCH] mmc: dw_mmc-pltfm: Fix usage of phase_map for SoCFPGA

[Brandt, Oliver - Lenze]

With a kernel 7.3.3 we saw the following on a SoCFPGA (Cyclone 5) based
board during initialization when using a high-speed SD-card:

  dw_mmc ff704000.mmc: DW MMC controller at irq 53,32 bit host data width,1024 deep fifo
  dw_mmc ff704000.mmc: Got CD GPIO
  dw_mmc ff704000.mmc: Got WP GPIO
  mmc_host mmc0: Bus speed = 50000000Hz (req 400000Hz, actual 396825HZ div = 63)
  mmc_host mmc0: Bus speed = 50000000Hz (req 50000000Hz, actual 50000000HZ div = 0)
  mmc0: error -110 whilst initialising SD card
  mmc_host mmc0: Bus speed = 50000000Hz (req 300000Hz, actual 297619HZ div = 84)
  mmc_host mmc0: Bus speed = 50000000Hz (req 50000000Hz, actual 50000000HZ div = 0)
  mmc0: error -110 whilst initialising SD card
  mmc_host mmc0: Bus speed = 50000000Hz (req 200000Hz, actual 200000HZ div = 125)
  mmc_host mmc0: Bus speed = 50000000Hz (req 50000000Hz, actual 50000000HZ div = 0)
  mmc0: error -110 whilst initialising SD card
  mmc_host mmc0: Bus speed = 50000000Hz (req 100000Hz, actual 100000HZ div = 250)
  mmc_host mmc0: Bus speed = 50000000Hz (req 50000000Hz, actual 50000000HZ div = 0)
  mmc0: error -110 whilst initialising SD card

The SD-card was not usable in the following.

Reason: Since commit 3f1628baa51e ("mmc: dw_mmc-pltfm: Use phase_map for
SoCFPGA clock phase configuration") host->phase_map is used in order to
get the phase settings for MMC_TIMING_SD_HS. This is done in drv_data->init
(dw_mci_socfpga_priv_init()) which is called before dw_mci_init_host(). As
host->phase_map will be initialized only during dw_mci_init_host(), we'll
call dw_mci_socfpga_priv_init() without the needed data.

Do it like other users of dw_mci_platfom and use drv_data->set_ios.

Fixes: 3f1628baa51e ("mmc: dw_mmc-pltfm: Use phase_map for SoCFPGA clock phase configuration")
Cc: stable@vger.kernel.org
Signed-off-by: Oliver Brandt <oliver.brandt@lenze.com>
---
 drivers/mmc/host/dw_mmc-pltfm.c | 13 +++++--------
 1 file changed, 5 insertions(+), 8 deletions(-)

diff --git a/drivers/mmc/host/dw_mmc-pltfm.c b/drivers/mmc/host/dw_mmc-pltfm.c
index cf38bb118dc2c..320d508881f48 100644
--- a/drivers/mmc/host/dw_mmc-pltfm.c
+++ b/drivers/mmc/host/dw_mmc-pltfm.c
@@ -56,7 +56,7 @@ int dw_mci_pltfm_register(struct platform_device *pdev,
 }
 EXPORT_SYMBOL_GPL(dw_mci_pltfm_register);
 
-static int dw_mci_socfpga_priv_init(struct dw_mci *host)
+static void dw_mci_socfpga_priv_set_ios(struct dw_mci *host, struct mmc_ios *ios)
 {
 	struct device_node *np = host->dev->of_node;
 	struct mmc_clk_phase phase;
@@ -64,14 +64,13 @@ static int dw_mci_socfpga_priv_init(struct dw_mci *host)
 	u32 reg_offset, reg_shift;
 	int hs_timing;
 
-	phase = host->phase_map.phase[MMC_TIMING_SD_HS];
-	if (!phase.valid)
-		return 0;
+	phase = host->phase_map.phase[ios->timing];
+	if ((ios->timing != MMC_TIMING_SD_HS) || !phase.valid)
+		return;
 
 	sys_mgr_base_addr = altr_sysmgr_regmap_lookup_by_phandle(np, "altr,sysmgr-syscon");
 	if (IS_ERR(sys_mgr_base_addr)) {
 		dev_warn(host->dev, "clk-phase-sd-hs was specified, but failed to find altr,sys-mgr regmap!\n");
-		return 0;
 	}
 
 	of_property_read_u32_index(np, "altr,sysmgr-syscon", 1, &reg_offset);
@@ -82,12 +81,10 @@ static int dw_mci_socfpga_priv_init(struct dw_mci *host)
 
 	hs_timing = SYSMGR_SDMMC_CTRL_SET(phase.in_deg, phase.out_deg, reg_shift);
 	regmap_write(sys_mgr_base_addr, reg_offset, hs_timing);
-
-	return 0;
 }
 
 static const struct dw_mci_drv_data socfpga_drv_data = {
-	.init		= dw_mci_socfpga_priv_init,
+	.set_ios	= dw_mci_socfpga_priv_set_ios,
 };
 
 static const struct of_device_id dw_mci_pltfm_match[] = {
-- 
2.47.3