* [PATCH v7 1/3] dt-bindings: mailbox: add google,gs101-mbox
2025-01-15 14:18 [PATCH v7 0/3] mailbox: add Samsung Exynos driver Tudor Ambarus
@ 2025-01-15 14:18 ` Tudor Ambarus
2025-01-15 19:44 ` Krzysztof Kozlowski
2025-01-15 14:18 ` [PATCH v7 2/3] mailbox: add Samsung Exynos driver Tudor Ambarus
` (2 subsequent siblings)
3 siblings, 1 reply; 6+ messages in thread
From: Tudor Ambarus @ 2025-01-15 14:18 UTC (permalink / raw)
To: Jassi Brar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krzysztof Kozlowski, Alim Akhtar
Cc: linux-kernel, linux-samsung-soc, devicetree, linux-arm-kernel,
andre.draszik, peter.griffin, kernel-team, willmcvicker,
daniel.lezcano, vincent.guittot, ulf.hansson, arnd,
Tudor Ambarus
Add bindings for the Samsung Exynos Mailbox Controller.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
.../bindings/mailbox/google,gs101-mbox.yaml | 69 ++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
new file mode 100644
index 000000000000..e249db4c1fbc
--- /dev/null
+++ b/Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
@@ -0,0 +1,69 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+# Copyright 2024 Linaro Ltd.
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/mailbox/google,gs101-mbox.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Samsung Exynos Mailbox Controller
+
+maintainers:
+ - Tudor Ambarus <tudor.ambarus@linaro.org>
+
+description:
+ The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16 flag
+ bits for hardware interrupt generation and a shared register for passing
+ mailbox messages. When the controller is used by the ACPM interface
+ the shared register is ignored and the mailbox controller acts as a doorbell.
+ The controller just raises the interrupt to the firmware after the
+ ACPM interface has written the message to SRAM.
+
+properties:
+ compatible:
+ const: google,gs101-mbox
+
+ reg:
+ maxItems: 1
+
+ clocks:
+ maxItems: 1
+
+ clock-names:
+ items:
+ - const: pclk
+
+ interrupts:
+ description: IRQ line for the RX mailbox.
+ maxItems: 1
+
+ '#mbox-cells':
+ const: 0
+
+required:
+ - compatible
+ - reg
+ - clocks
+ - clock-names
+ - interrupts
+ - '#mbox-cells'
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/interrupt-controller/arm-gic.h>
+ #include <dt-bindings/clock/google,gs101.h>
+
+ soc {
+ #address-cells = <1>;
+ #size-cells = <1>;
+
+ ap2apm_mailbox: mailbox@17610000 {
+ compatible = "google,gs101-mbox";
+ reg = <0x17610000 0x1000>;
+ clocks = <&cmu_apm CLK_GOUT_APM_MAILBOX_APM_AP_PCLK>;
+ clock-names = "pclk";
+ interrupts = <GIC_SPI 73 IRQ_TYPE_LEVEL_HIGH 0>;
+ #mbox-cells = <0>;
+ };
+ };
--
2.48.0.rc2.279.g1de40edade-goog
^ permalink raw reply [flat|nested] 6+ messages in thread* Re: [PATCH v7 1/3] dt-bindings: mailbox: add google,gs101-mbox
2025-01-15 14:18 ` [PATCH v7 1/3] dt-bindings: mailbox: add google,gs101-mbox Tudor Ambarus
@ 2025-01-15 19:44 ` Krzysztof Kozlowski
0 siblings, 0 replies; 6+ messages in thread
From: Krzysztof Kozlowski @ 2025-01-15 19:44 UTC (permalink / raw)
To: Tudor Ambarus, Jassi Brar, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Alim Akhtar
Cc: linux-kernel, linux-samsung-soc, devicetree, linux-arm-kernel,
andre.draszik, peter.griffin, kernel-team, willmcvicker,
daniel.lezcano, vincent.guittot, ulf.hansson, arnd
On 15/01/2025 15:18, Tudor Ambarus wrote:
> Add bindings for the Samsung Exynos Mailbox Controller.
>
> Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
> ---
> .../bindings/mailbox/google,gs101-mbox.yaml | 69 ++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v7 2/3] mailbox: add Samsung Exynos driver
2025-01-15 14:18 [PATCH v7 0/3] mailbox: add Samsung Exynos driver Tudor Ambarus
2025-01-15 14:18 ` [PATCH v7 1/3] dt-bindings: mailbox: add google,gs101-mbox Tudor Ambarus
@ 2025-01-15 14:18 ` Tudor Ambarus
2025-01-15 14:18 ` [PATCH v7 3/3] MAINTAINERS: add entry for Samsung Exynos mailbox driver Tudor Ambarus
2025-01-15 17:22 ` [PATCH v7 0/3] mailbox: add Samsung Exynos driver Jassi Brar
3 siblings, 0 replies; 6+ messages in thread
From: Tudor Ambarus @ 2025-01-15 14:18 UTC (permalink / raw)
To: Jassi Brar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krzysztof Kozlowski, Alim Akhtar
Cc: linux-kernel, linux-samsung-soc, devicetree, linux-arm-kernel,
andre.draszik, peter.griffin, kernel-team, willmcvicker,
daniel.lezcano, vincent.guittot, ulf.hansson, arnd,
Tudor Ambarus
The Samsung Exynos mailbox controller, used on Google GS101 SoC, has 16
flag bits for hardware interrupt generation and a shared register for
passing mailbox messages. When the controller is used by the
ACPM interface the shared register is ignored and the mailbox controller
acts as a doorbell. The controller just raises the interrupt to APM
after the ACPM interface has written the message to SRAM.
Add support for the Samsung Exynos mailbox controller.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
---
drivers/mailbox/Kconfig | 11 +++
drivers/mailbox/Makefile | 2 +
drivers/mailbox/exynos-mailbox.c | 157 +++++++++++++++++++++++++++++++++
include/linux/mailbox/exynos-message.h | 19 ++++
4 files changed, 189 insertions(+)
diff --git a/drivers/mailbox/Kconfig b/drivers/mailbox/Kconfig
index 8ecba7fb999e..3d2adece9ded 100644
--- a/drivers/mailbox/Kconfig
+++ b/drivers/mailbox/Kconfig
@@ -36,6 +36,17 @@ config ARM_MHU_V3
that provides different means of transports: supported extensions
will be discovered and possibly managed at probe-time.
+config EXYNOS_MBOX
+ tristate "Exynos Mailbox"
+ depends on ARCH_EXYNOS || COMPILE_TEST
+ help
+ Say Y here if you want to build the Samsung Exynos Mailbox controller
+ driver. The controller has 16 flag bits for hardware interrupt
+ generation and a shared register for passing mailbox messages.
+ When the controller is used by the ACPM interface the shared register
+ is ignored and the mailbox controller acts as a doorbell that raises
+ the interrupt to the ACPM firmware.
+
config IMX_MBOX
tristate "i.MX Mailbox"
depends on ARCH_MXC || COMPILE_TEST
diff --git a/drivers/mailbox/Makefile b/drivers/mailbox/Makefile
index 5f4f5b0ce2cc..86192b5c7c32 100644
--- a/drivers/mailbox/Makefile
+++ b/drivers/mailbox/Makefile
@@ -11,6 +11,8 @@ obj-$(CONFIG_ARM_MHU_V2) += arm_mhuv2.o
obj-$(CONFIG_ARM_MHU_V3) += arm_mhuv3.o
+obj-$(CONFIG_EXYNOS_MBOX) += exynos-mailbox.o
+
obj-$(CONFIG_IMX_MBOX) += imx-mailbox.o
obj-$(CONFIG_ARMADA_37XX_RWTM_MBOX) += armada-37xx-rwtm-mailbox.o
diff --git a/drivers/mailbox/exynos-mailbox.c b/drivers/mailbox/exynos-mailbox.c
new file mode 100644
index 000000000000..20049f0ec5ff
--- /dev/null
+++ b/drivers/mailbox/exynos-mailbox.c
@@ -0,0 +1,157 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright 2020 Samsung Electronics Co., Ltd.
+ * Copyright 2020 Google LLC.
+ * Copyright 2024 Linaro Ltd.
+ */
+
+#include <linux/bitops.h>
+#include <linux/bits.h>
+#include <linux/clk.h>
+#include <linux/io.h>
+#include <linux/mailbox_controller.h>
+#include <linux/mailbox/exynos-message.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/platform_device.h>
+#include <linux/slab.h>
+
+#define EXYNOS_MBOX_MCUCTRL 0x0 /* Mailbox Control Register */
+#define EXYNOS_MBOX_INTCR0 0x24 /* Interrupt Clear Register 0 */
+#define EXYNOS_MBOX_INTMR0 0x28 /* Interrupt Mask Register 0 */
+#define EXYNOS_MBOX_INTSR0 0x2c /* Interrupt Status Register 0 */
+#define EXYNOS_MBOX_INTMSR0 0x30 /* Interrupt Mask Status Register 0 */
+#define EXYNOS_MBOX_INTGR1 0x40 /* Interrupt Generation Register 1 */
+#define EXYNOS_MBOX_INTMR1 0x48 /* Interrupt Mask Register 1 */
+#define EXYNOS_MBOX_INTSR1 0x4c /* Interrupt Status Register 1 */
+#define EXYNOS_MBOX_INTMSR1 0x50 /* Interrupt Mask Status Register 1 */
+
+#define EXYNOS_MBOX_INTMR0_MASK GENMASK(15, 0)
+#define EXYNOS_MBOX_INTGR1_MASK GENMASK(15, 0)
+
+#define EXYNOS_MBOX_CHAN_COUNT HWEIGHT32(EXYNOS_MBOX_INTGR1_MASK)
+
+/**
+ * struct exynos_mbox - driver's private data.
+ * @regs: mailbox registers base address.
+ * @mbox: pointer to the mailbox controller.
+ * @pclk: pointer to the mailbox peripheral clock.
+ */
+struct exynos_mbox {
+ void __iomem *regs;
+ struct mbox_controller *mbox;
+ struct clk *pclk;
+};
+
+static int exynos_mbox_send_data(struct mbox_chan *chan, void *data)
+{
+ struct device *dev = chan->mbox->dev;
+ struct exynos_mbox *exynos_mbox = dev_get_drvdata(dev);
+ struct exynos_mbox_msg *msg = data;
+
+ if (msg->chan_id >= exynos_mbox->mbox->num_chans) {
+ dev_err(dev, "Invalid channel ID %d\n", msg->chan_id);
+ return -EINVAL;
+ }
+
+ if (msg->chan_type != EXYNOS_MBOX_CHAN_TYPE_DOORBELL) {
+ dev_err(dev, "Unsupported channel type [%d]\n", msg->chan_type);
+ return -EINVAL;
+ };
+
+ writel(BIT(msg->chan_id), exynos_mbox->regs + EXYNOS_MBOX_INTGR1);
+
+ return 0;
+}
+
+static const struct mbox_chan_ops exynos_mbox_chan_ops = {
+ .send_data = exynos_mbox_send_data,
+};
+
+static struct mbox_chan *exynos_mbox_of_xlate(struct mbox_controller *mbox,
+ const struct of_phandle_args *sp)
+{
+ int i;
+
+ if (sp->args_count != 0)
+ return ERR_PTR(-EINVAL);
+
+ /*
+ * Return the first available channel. When we don't pass the
+ * channel ID from device tree, each channel populated by the driver is
+ * just a software construct or a virtual channel. We use 'void *data'
+ * in send_data() to pass the channel identifiers.
+ */
+ for (i = 0; i < mbox->num_chans; i++)
+ if (mbox->chans[i].cl == NULL)
+ return &mbox->chans[i];
+ return ERR_PTR(-EINVAL);
+}
+
+static const struct of_device_id exynos_mbox_match[] = {
+ { .compatible = "google,gs101-mbox" },
+ {},
+};
+MODULE_DEVICE_TABLE(of, exynos_mbox_match);
+
+static int exynos_mbox_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct exynos_mbox *exynos_mbox;
+ struct mbox_controller *mbox;
+ struct mbox_chan *chans;
+ int i;
+
+ exynos_mbox = devm_kzalloc(dev, sizeof(*exynos_mbox), GFP_KERNEL);
+ if (!exynos_mbox)
+ return -ENOMEM;
+
+ mbox = devm_kzalloc(dev, sizeof(*mbox), GFP_KERNEL);
+ if (!mbox)
+ return -ENOMEM;
+
+ chans = devm_kcalloc(dev, EXYNOS_MBOX_CHAN_COUNT, sizeof(*chans),
+ GFP_KERNEL);
+ if (!chans)
+ return -ENOMEM;
+
+ exynos_mbox->regs = devm_platform_ioremap_resource(pdev, 0);
+ if (IS_ERR(exynos_mbox->regs))
+ return PTR_ERR(exynos_mbox->regs);
+
+ exynos_mbox->pclk = devm_clk_get_enabled(dev, "pclk");
+ if (IS_ERR(exynos_mbox->pclk))
+ return dev_err_probe(dev, PTR_ERR(exynos_mbox->pclk),
+ "Failed to enable clock.\n");
+
+ mbox->num_chans = EXYNOS_MBOX_CHAN_COUNT;
+ mbox->chans = chans;
+ mbox->dev = dev;
+ mbox->ops = &exynos_mbox_chan_ops;
+ mbox->of_xlate = exynos_mbox_of_xlate;
+
+ for (i = 0; i < EXYNOS_MBOX_CHAN_COUNT; i++)
+ chans[i].mbox = mbox;
+
+ exynos_mbox->mbox = mbox;
+
+ platform_set_drvdata(pdev, exynos_mbox);
+
+ /* Mask out all interrupts. We support just polling channels for now. */
+ writel(EXYNOS_MBOX_INTMR0_MASK, exynos_mbox->regs + EXYNOS_MBOX_INTMR0);
+
+ return devm_mbox_controller_register(dev, mbox);
+}
+
+static struct platform_driver exynos_mbox_driver = {
+ .probe = exynos_mbox_probe,
+ .driver = {
+ .name = "exynos-acpm-mbox",
+ .of_match_table = exynos_mbox_match,
+ },
+};
+module_platform_driver(exynos_mbox_driver);
+
+MODULE_AUTHOR("Tudor Ambarus <tudor.ambarus@linaro.org>");
+MODULE_DESCRIPTION("Samsung Exynos mailbox driver");
+MODULE_LICENSE("GPL");
diff --git a/include/linux/mailbox/exynos-message.h b/include/linux/mailbox/exynos-message.h
new file mode 100644
index 000000000000..5a9ed5ce2046
--- /dev/null
+++ b/include/linux/mailbox/exynos-message.h
@@ -0,0 +1,19 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+/*
+ * Exynos mailbox message.
+ *
+ * Copyright 2024 Linaro Ltd.
+ */
+
+#ifndef _LINUX_EXYNOS_MESSAGE_H_
+#define _LINUX_EXYNOS_MESSAGE_H_
+
+#define EXYNOS_MBOX_CHAN_TYPE_DOORBELL 0
+#define EXYNOS_MBOX_CHAN_TYPE_DATA 1
+
+struct exynos_mbox_msg {
+ unsigned int chan_id;
+ unsigned int chan_type;
+};
+
+#endif /* _LINUX_EXYNOS_MESSAGE_H_ */
--
2.48.0.rc2.279.g1de40edade-goog
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v7 3/3] MAINTAINERS: add entry for Samsung Exynos mailbox driver
2025-01-15 14:18 [PATCH v7 0/3] mailbox: add Samsung Exynos driver Tudor Ambarus
2025-01-15 14:18 ` [PATCH v7 1/3] dt-bindings: mailbox: add google,gs101-mbox Tudor Ambarus
2025-01-15 14:18 ` [PATCH v7 2/3] mailbox: add Samsung Exynos driver Tudor Ambarus
@ 2025-01-15 14:18 ` Tudor Ambarus
2025-01-15 17:22 ` [PATCH v7 0/3] mailbox: add Samsung Exynos driver Jassi Brar
3 siblings, 0 replies; 6+ messages in thread
From: Tudor Ambarus @ 2025-01-15 14:18 UTC (permalink / raw)
To: Jassi Brar, Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krzysztof Kozlowski, Alim Akhtar
Cc: linux-kernel, linux-samsung-soc, devicetree, linux-arm-kernel,
andre.draszik, peter.griffin, kernel-team, willmcvicker,
daniel.lezcano, vincent.guittot, ulf.hansson, arnd,
Tudor Ambarus, Krzysztof Kozlowski
Add entry for the Samsung Exynos mailbox driver.
Signed-off-by: Tudor Ambarus <tudor.ambarus@linaro.org>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Reviewed-by: Peter Griffin <peter.griffin@linaro.org>
---
MAINTAINERS | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/MAINTAINERS b/MAINTAINERS
index a87ddad78e26..20163d8a8d90 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -3020,6 +3020,7 @@ F: drivers/*/*s3c24*
F: drivers/*/*s3c64xx*
F: drivers/*/*s5pv210*
F: drivers/clocksource/samsung_pwm_timer.c
+F: drivers/mailbox/exynos-mailbox.c
F: drivers/memory/samsung/
F: drivers/pwm/pwm-samsung.c
F: drivers/soc/samsung/
@@ -20712,6 +20713,15 @@ F: arch/arm64/boot/dts/exynos/exynos850*
F: drivers/clk/samsung/clk-exynos850.c
F: include/dt-bindings/clock/exynos850.h
+SAMSUNG EXYNOS MAILBOX DRIVER
+M: Tudor Ambarus <tudor.ambarus@linaro.org>
+L: linux-kernel@vger.kernel.org
+L: linux-samsung-soc@vger.kernel.org
+S: Supported
+F: Documentation/devicetree/bindings/mailbox/google,gs101-mbox.yaml
+F: drivers/mailbox/exynos-mailbox.c
+F: include/linux/mailbox/exynos-message.h
+
SAMSUNG EXYNOS PSEUDO RANDOM NUMBER GENERATOR (RNG) DRIVER
M: Krzysztof Kozlowski <krzk@kernel.org>
L: linux-crypto@vger.kernel.org
--
2.48.0.rc2.279.g1de40edade-goog
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v7 0/3] mailbox: add Samsung Exynos driver
2025-01-15 14:18 [PATCH v7 0/3] mailbox: add Samsung Exynos driver Tudor Ambarus
` (2 preceding siblings ...)
2025-01-15 14:18 ` [PATCH v7 3/3] MAINTAINERS: add entry for Samsung Exynos mailbox driver Tudor Ambarus
@ 2025-01-15 17:22 ` Jassi Brar
3 siblings, 0 replies; 6+ messages in thread
From: Jassi Brar @ 2025-01-15 17:22 UTC (permalink / raw)
To: Tudor Ambarus
Cc: Rob Herring, Krzysztof Kozlowski, Conor Dooley,
Krzysztof Kozlowski, Alim Akhtar, linux-kernel,
linux-samsung-soc, devicetree, linux-arm-kernel, andre.draszik,
peter.griffin, kernel-team, willmcvicker, daniel.lezcano,
vincent.guittot, ulf.hansson, arnd, Krzysztof Kozlowski
On Wed, Jan 15, 2025 at 8:18 AM Tudor Ambarus <tudor.ambarus@linaro.org> wrote:
>
> Hi,
>
> Now that the channel identifiers are passed through 'void *data' in
> send_data(), the clients now depend on the message format introduced in
> include/linux/mailbox/exynos-message.h. If Jassi finds this set fine,
> then he shall provide either an immutable tag so that Krzysztof uses it
> if applying the ACPM interface driver, or to ACK this set and let Krzysztof
> queue it.
>
v6 => 11 files changed, 366 insertions(+), 2 deletions(-)
v7 => 6 files changed, 268 insertions(+)
Awesome! we have far fewer changes and no new api added.
I will queue the driver.
Cheers!
^ permalink raw reply [flat|nested] 6+ messages in thread