* [PATCH] perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline
@ 2022-08-16 11:40 Like Xu
2022-08-16 12:04 ` Liang, Kan
2022-08-22 9:00 ` [tip: perf/urgent] " tip-bot2 for Peter Zijlstra
0 siblings, 2 replies; 3+ messages in thread
From: Like Xu @ 2022-08-16 11:40 UTC (permalink / raw)
To: Peter Zijlstra
Cc: Kan Liang, Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, x86,
linux-perf-users, linux-kernel
From: Peter Zijlstra <peterz@infradead.org>
The SDM explicitly states that PEBS Baseline implies Extended PEBS.
For cpu model forward compatibility (e.g. on ICX, SPR, ADL), it's
safe to stop doing FMS table thing such as setting pebs_capable and
PMU_FL_PEBS_ALL since it's already set in the intel_ds_init().
The Goldmont Plus is the only platform which supports extended PEBS
but doesn't have Baseline. Keep the status quo.
Cc: Kan Liang <kan.liang@linux.intel.com>
Reported-by: Like Xu <likexu@tencent.com>
Signed-off-by: Peter Zijlstra <peterz@infradead.org>
---
arch/x86/events/intel/core.c | 4 ----
arch/x86/events/intel/ds.c | 1 +
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2db93498ff71..cb98a05ee743 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6291,10 +6291,8 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
- x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
@@ -6337,10 +6335,8 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
- x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
x86_pmu.lbr_pt_coexist = true;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ba60427caa6d..ac6dd4c96dbc 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2262,6 +2262,7 @@ void __init intel_ds_init(void)
PERF_SAMPLE_BRANCH_STACK |
PERF_SAMPLE_TIME;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
+ x86_pmu.pebs_capable = ~0ULL;
pebs_qual = "-baseline";
x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
} else {
--
2.37.2
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline
2022-08-16 11:40 [PATCH] perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline Like Xu
@ 2022-08-16 12:04 ` Liang, Kan
2022-08-22 9:00 ` [tip: perf/urgent] " tip-bot2 for Peter Zijlstra
1 sibling, 0 replies; 3+ messages in thread
From: Liang, Kan @ 2022-08-16 12:04 UTC (permalink / raw)
To: Like Xu, Peter Zijlstra
Cc: Ingo Molnar, Arnaldo Carvalho de Melo, Mark Rutland,
Alexander Shishkin, Jiri Olsa, Namhyung Kim, x86,
linux-perf-users, linux-kernel
On 2022-08-16 7:40 a.m., Like Xu wrote:
> From: Peter Zijlstra <peterz@infradead.org>
>
> The SDM explicitly states that PEBS Baseline implies Extended PEBS.
> For cpu model forward compatibility (e.g. on ICX, SPR, ADL), it's
> safe to stop doing FMS table thing such as setting pebs_capable and
> PMU_FL_PEBS_ALL since it's already set in the intel_ds_init().
>
> The Goldmont Plus is the only platform which supports extended PEBS
> but doesn't have Baseline. Keep the status quo.
>
> Cc: Kan Liang <kan.liang@linux.intel.com>
> Reported-by: Like Xu <likexu@tencent.com>
> Signed-off-by: Peter Zijlstra <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Thanks,
Kan
> ---
> arch/x86/events/intel/core.c | 4 ----
> arch/x86/events/intel/ds.c | 1 +
> 2 files changed, 1 insertion(+), 4 deletions(-)
>
> diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
> index 2db93498ff71..cb98a05ee743 100644
> --- a/arch/x86/events/intel/core.c
> +++ b/arch/x86/events/intel/core.c
> @@ -6291,10 +6291,8 @@ __init int intel_pmu_init(void)
> x86_pmu.pebs_aliases = NULL;
> x86_pmu.pebs_prec_dist = true;
> x86_pmu.pebs_block = true;
> - x86_pmu.pebs_capable = ~0ULL;
> x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
> - x86_pmu.flags |= PMU_FL_PEBS_ALL;
> x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
> x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
>
> @@ -6337,10 +6335,8 @@ __init int intel_pmu_init(void)
> x86_pmu.pebs_aliases = NULL;
> x86_pmu.pebs_prec_dist = true;
> x86_pmu.pebs_block = true;
> - x86_pmu.pebs_capable = ~0ULL;
> x86_pmu.flags |= PMU_FL_HAS_RSP_1;
> x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
> - x86_pmu.flags |= PMU_FL_PEBS_ALL;
> x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
> x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
> x86_pmu.lbr_pt_coexist = true;
> diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
> index ba60427caa6d..ac6dd4c96dbc 100644
> --- a/arch/x86/events/intel/ds.c
> +++ b/arch/x86/events/intel/ds.c
> @@ -2262,6 +2262,7 @@ void __init intel_ds_init(void)
> PERF_SAMPLE_BRANCH_STACK |
> PERF_SAMPLE_TIME;
> x86_pmu.flags |= PMU_FL_PEBS_ALL;
> + x86_pmu.pebs_capable = ~0ULL;
> pebs_qual = "-baseline";
> x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
> } else {
^ permalink raw reply [flat|nested] 3+ messages in thread
* [tip: perf/urgent] perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline
2022-08-16 11:40 [PATCH] perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline Like Xu
2022-08-16 12:04 ` Liang, Kan
@ 2022-08-22 9:00 ` tip-bot2 for Peter Zijlstra
1 sibling, 0 replies; 3+ messages in thread
From: tip-bot2 for Peter Zijlstra @ 2022-08-22 9:00 UTC (permalink / raw)
To: linux-tip-commits
Cc: Like Xu, Peter Zijlstra (Intel), Kan Liang, x86, linux-kernel
The following commit has been merged into the perf/urgent branch of tip:
Commit-ID: 7d3598868aaee05eb738d1c3115616b867e7530a
Gitweb: https://git.kernel.org/tip/7d3598868aaee05eb738d1c3115616b867e7530a
Author: Peter Zijlstra <peterz@infradead.org>
AuthorDate: Tue, 16 Aug 2022 19:40:57 +08:00
Committer: Peter Zijlstra <peterz@infradead.org>
CommitterDate: Fri, 19 Aug 2022 19:47:31 +02:00
perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline
The SDM explicitly states that PEBS Baseline implies Extended PEBS.
For cpu model forward compatibility (e.g. on ICX, SPR, ADL), it's
safe to stop doing FMS table thing such as setting pebs_capable and
PMU_FL_PEBS_ALL since it's already set in the intel_ds_init().
The Goldmont Plus is the only platform which supports extended PEBS
but doesn't have Baseline. Keep the status quo.
Reported-by: Like Xu <likexu@tencent.com>
Signed-off-by: Peter Zijlstra (Intel) <peterz@infradead.org>
Reviewed-by: Kan Liang <kan.liang@linux.intel.com>
Link: https://lkml.kernel.org/r/20220816114057.51307-1-likexu@tencent.com
---
arch/x86/events/intel/core.c | 4 ----
arch/x86/events/intel/ds.c | 1 +
2 files changed, 1 insertion(+), 4 deletions(-)
diff --git a/arch/x86/events/intel/core.c b/arch/x86/events/intel/core.c
index 2db9349..cb98a05 100644
--- a/arch/x86/events/intel/core.c
+++ b/arch/x86/events/intel/core.c
@@ -6291,10 +6291,8 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
- x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
@@ -6337,10 +6335,8 @@ __init int intel_pmu_init(void)
x86_pmu.pebs_aliases = NULL;
x86_pmu.pebs_prec_dist = true;
x86_pmu.pebs_block = true;
- x86_pmu.pebs_capable = ~0ULL;
x86_pmu.flags |= PMU_FL_HAS_RSP_1;
x86_pmu.flags |= PMU_FL_NO_HT_SHARING;
- x86_pmu.flags |= PMU_FL_PEBS_ALL;
x86_pmu.flags |= PMU_FL_INSTR_LATENCY;
x86_pmu.flags |= PMU_FL_MEM_LOADS_AUX;
x86_pmu.lbr_pt_coexist = true;
diff --git a/arch/x86/events/intel/ds.c b/arch/x86/events/intel/ds.c
index ba60427..ac6dd4c 100644
--- a/arch/x86/events/intel/ds.c
+++ b/arch/x86/events/intel/ds.c
@@ -2262,6 +2262,7 @@ void __init intel_ds_init(void)
PERF_SAMPLE_BRANCH_STACK |
PERF_SAMPLE_TIME;
x86_pmu.flags |= PMU_FL_PEBS_ALL;
+ x86_pmu.pebs_capable = ~0ULL;
pebs_qual = "-baseline";
x86_get_pmu(smp_processor_id())->capabilities |= PERF_PMU_CAP_EXTENDED_REGS;
} else {
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-08-22 9:01 UTC | newest]
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2022-08-16 11:40 [PATCH] perf/x86/core: Set pebs_capable and PMU_FL_PEBS_ALL for the Baseline Like Xu
2022-08-16 12:04 ` Liang, Kan
2022-08-22 9:00 ` [tip: perf/urgent] " tip-bot2 for Peter Zijlstra
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