From: Jianjun Wang <jianjun.wang@mediatek.com>
To: AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com>,
Chunfeng Yun <chunfeng.yun@mediatek.com>,
Kishon Vijay Abraham I <kishon@ti.com>,
Vinod Koul <vkoul@kernel.org>, Rob Herring <robh+dt@kernel.org>,
Matthias Brugger <matthias.bgg@gmail.com>,
"Chen-Yu Tsai" <wenst@chromium.org>,
Krzysztof Kozlowski <krzk@kernel.org>
Cc: Wei-Shun Chang <weishunc@google.com>,
<linux-arm-kernel@lists.infradead.org>,
<linux-mediatek@lists.infradead.org>,
<linux-phy@lists.infradead.org>, <devicetree@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <rex-bc.chen@mediatek.com>,
<randy.wu@mediatek.com>, <jieyy.yang@mediatek.com>,
<chuanjia.liu@mediatek.com>, <qizhong.cheng@mediatek.com>,
<jian.yang@mediatek.com>
Subject: Re: [PATCH v4 2/2] phy: mediatek: Add PCIe PHY driver
Date: Sat, 26 Mar 2022 09:56:26 +0800 [thread overview]
Message-ID: <2ceb84aec51252cfb254525900480cc380fc2c03.camel@mediatek.com> (raw)
In-Reply-To: <be06e57d-302e-e641-a134-c45ea89a6a6b@collabora.com>
On Fri, 2022-03-25 at 15:15 +0100, AngeloGioacchino Del Regno wrote:
> Il 23/03/22 07:56, Jianjun Wang ha scritto:
> > Add PCIe GEN3 PHY driver support on MediaTek chipsets.
> >
> > Signed-off-by: Jianjun Wang <jianjun.wang@mediatek.com>
> > ---
> > drivers/phy/mediatek/Kconfig | 11 ++
> > drivers/phy/mediatek/Makefile | 1 +
> > drivers/phy/mediatek/phy-mtk-pcie.c | 272
> > ++++++++++++++++++++++++++++
> > 3 files changed, 284 insertions(+)
> > create mode 100644 drivers/phy/mediatek/phy-mtk-pcie.c
> >
>
> ..snip..
>
> > diff --git a/drivers/phy/mediatek/phy-mtk-pcie.c
> > b/drivers/phy/mediatek/phy-mtk-pcie.c
> > new file mode 100644
> > index 000000000000..44a2ad8d324e
> > --- /dev/null
> > +++ b/drivers/phy/mediatek/phy-mtk-pcie.c
> > @@ -0,0 +1,272 @@
>
> ..snip..
>
> > +/**
> > + * struct mtk_pcie_phy - PCIe phy driver main structure
> > + * @dev: pointer to device
> > + * @phy: pointer to generic phy
> > + * @sif_base: IO mapped register base address of system interface
> > + * @data: pointer to SoC dependent data
> > + * @sw_efuse_en: software eFuse enable status
> > + * @efuse_glb_intr: internal resistor selection of TX bias current
> > data
> > + * @efuse: pointer to eFues data for each lane
>
> Oops! There's a typo! "eFues" => "eFuse"
>
> After fixing this typo,
>
> Reviewed-by: AngeloGioacchino Del Regno <
> angelogioacchino.delregno@collabora.com>
Thanks!
>
> P.S.: Many thanks for the kerneldoc documentation!!!!
>
> > + */
> > +struct mtk_pcie_phy {
> > + struct device *dev;
> > + struct phy *phy;
> > + void __iomem *sif_base;
> > + const struct mtk_pcie_phy_data *data;
> > +
> > + bool sw_efuse_en;
> > + u32 efuse_glb_intr;
> > + struct mtk_pcie_lane_efuse *efuse;
> > +};
>
>
prev parent reply other threads:[~2022-03-26 1:56 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-23 6:56 [PATCH v4 0/2] " Jianjun Wang
2022-03-23 6:56 ` [PATCH v4 1/2] dt-bindings: phy: mediatek: Add YAML schema for PCIe PHY Jianjun Wang
2022-03-23 6:56 ` [PATCH v4 2/2] phy: mediatek: Add PCIe PHY driver Jianjun Wang
2022-03-25 14:15 ` AngeloGioacchino Del Regno
2022-03-26 1:56 ` Jianjun Wang [this message]
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