* [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards
@ 2025-09-08 13:05 Mateusz Koza
2025-09-08 13:05 ` [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Mateusz Koza
` (4 more replies)
0 siblings, 5 replies; 10+ messages in thread
From: Mateusz Koza @ 2025-09-08 13:05 UTC (permalink / raw)
To: angelogioacchino.delregno, robh
Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel,
linux-mediatek, devicetree, marcin.czarnecki, b.bilas,
mateusz.koza, andrew
This patch series adds support for Grinn GenioSBC-510 and GenioSBC-700
boards based on MediaTek MT8370 and MT8390 SoCs, respectively. It
includes device tree files for both boards, updates to the device tree
bindings, and necessary modifications to the Makefile.
As far as I know, <angelogioacchino.delregno@collabora.com> has access
to the schematics for these boards, as we've shared them under NDA with
Collabora.
Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com>
---
v2: Fixed the subject prefixes,
Fixed alignment in dts files,
Added missing SPDX-License-Identifier,
Fixed the ordering in dt-bindings,
Dropped redundant info from commit messages,
Run checkpatch.pl on the patchset and fixed the issues,
as suggested by Krzysztof Kozlowski <krzk@kernel.org>.
v3: Changed eth phy-mode to 'rgmii-id',
Changed eth mediatek,tx-delay-ps to 30,
as suggested by Andrew Lunn <andrew@lunn.ch>.
v4: Removed the nodes that are not present in upstream,
as suggested by Louis-Alexis <angelogioacchino.delregno@collabora.com>.
Added default pinctrl to ssusb0,
Enabled the scp_cluster node,
as suggested by Bartosz Biłas <b.bilas@grinn-global.com>.
---
Bartosz Bilas (1):
arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn
GenioSBC-510
Mateusz Koza (3):
arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700
dt-bindings: arm: mediatek: Add grinn,genio-700-sbc
dt-bindings: arm: mediatek: Add grinn,genio-510-sbc
.../devicetree/bindings/arm/mediatek.yaml | 2 +
arch/arm64/boot/dts/mediatek/Makefile | 2 +
.../mediatek/mt8370-grinn-genio-510-sbc.dts | 19 +
.../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 +
.../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 538 ++++++++++++++++++
.../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 +++++++
6 files changed, 789 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi
create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi
--
2.43.0
^ permalink raw reply [flat|nested] 10+ messages in thread* [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 2025-09-08 13:05 [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Mateusz Koza @ 2025-09-08 13:05 ` Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-08 13:05 ` [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Mateusz Koza ` (3 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Mateusz Koza @ 2025-09-08 13:05 UTC (permalink / raw) To: angelogioacchino.delregno, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, mateusz.koza, andrew Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a single-board computer based on the MediaTek Genio 700 SoC. Its device tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are combined in the SoC-specific .dts file. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Reviewed-by: Andrew Lunn <andrew@lunn.ch> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 + .../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 538 ++++++++++++++++++ .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 +++++++ 4 files changed, 767 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index a4df4c21399e..b37a8c65e724 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts new file mode 100644 index 000000000000..a37507a5a5d0 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza <mateusz.koza@grinn-global.com> + */ +/dts-v1/; + +#include "mt8188.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model = "Grinn GenioSBC-700"; + compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188"; + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 1 0x00000000>; + }; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi new file mode 100644 index 000000000000..0e6006cd8ed9 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi @@ -0,0 +1,538 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza <mateusz.koza@grinn-global.com> + */ + +#include <dt-bindings/gpio/gpio.h> + +/ { + chassis-type = "embedded"; + aliases { + ethernet0 = ð + i2c0 = &i2c0; + i2c2 = &i2c2; + i2c3 = &i2c3; + i2c5 = &i2c5; + i2c6 = &i2c6; + serial0 = &uart0; + }; + + chosen { + stdout-path = "serial0:921600n8"; + }; + + firmware { + optee { + compatible = "linaro,optee-tz"; + method = "smc"; + }; + }; + + reserved-memory { + #address-cells = <2>; + #size-cells = <2>; + ranges; + + /* + * 12 MiB reserved for OP-TEE (BL32) + * +-----------------------+ 0x43e0_0000 + * | SHMEM 2MiB | + * +-----------------------+ 0x43c0_0000 + * | | TA_RAM 8MiB | + * + TZDRAM +--------------+ 0x4340_0000 + * | | TEE_RAM 2MiB | + * +-----------------------+ 0x4320_0000 + */ + optee_reserved: optee@43200000 { + no-map; + reg = <0 0x43200000 0 0x00c00000>; + }; + + scp_mem: memory@50000000 { + compatible = "shared-dma-pool"; + reg = <0 0x50000000 0 0x2900000>; + no-map; + }; + + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ + bl31_secmon_reserved: memory@54600000 { + no-map; + reg = <0 0x54600000 0x0 0x200000>; + }; + + apu_mem: memory@55000000 { + compatible = "shared-dma-pool"; + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ + }; + + vpu_mem: memory@57000000 { + compatible = "shared-dma-pool"; + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ + }; + + adsp_mem: memory@60000000 { + compatible = "shared-dma-pool"; + reg = <0 0x60000000 0 0xf00000>; + no-map; + }; + + afe_dma_mem: memory@60f00000 { + compatible = "shared-dma-pool"; + reg = <0 0x60f00000 0 0x100000>; + no-map; + }; + + adsp_dma_mem: memory@61000000 { + compatible = "shared-dma-pool"; + reg = <0 0x61000000 0 0x100000>; + no-map; + }; + }; + + reg_sbc_vsys: regulator-vsys { + compatible = "regulator-fixed"; + regulator-name = "vsys"; + regulator-always-on; + regulator-boot-on; + }; + + reg_fixed_5v: regulator-0 { + compatible = "regulator-fixed"; + regulator-name = "fixed_5v"; + regulator-min-microvolt = <5000000>; + regulator-max-microvolt = <5000000>; + enable-active-high; + regulator-always-on; + vin-supply = <®_sbc_vsys>; + }; + + reg_fixed_4v2: regulator-1 { + compatible = "regulator-fixed"; + regulator-name = "fixed_4v2"; + regulator-min-microvolt = <4200000>; + regulator-max-microvolt = <4200000>; + enable-active-high; + regulator-always-on; + vin-supply = <®_sbc_vsys>; + }; + + reg_fixed_3v3: regulator-2 { + compatible = "regulator-fixed"; + regulator-name = "fixed_3v3"; + regulator-min-microvolt = <3300000>; + regulator-max-microvolt = <3300000>; + enable-active-high; + regulator-always-on; + vin-supply = <®_sbc_vsys>; + }; +}; + +&pio { + gpio-line-names = + /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4", + /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9", + /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "", + /* 15 - 19 */ "", "", "", "", "", + /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "", + /* 25 - 29 */ "", "", "", "", "", + /* 30 - 34 */ "RPI_GPIO30", "", "", "", "", + /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "", + /* 40 - 44 */ "", "", "", "", "", + /* 45 - 49 */ "", "", "", "", "", + /* 50 - 54 */ "", "", "", "", "", + /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59", + /* 60 - 64 */ "RPI_GPIO60", "", "", "", "", + /* 65 - 69 */ "", "", "", "", "RPI_GPIO69", + /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74", + /* 75 - 79 */ "", "", "", "", "RPI_GPIO79", + /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "", + /* 85 - 89 */ "", "", "", "", "", + /* 90 - 94 */ "", "", "", "", "", + /* 95 - 99 */ "", "", "", "", "", + /*100 - 104 */ "", "", "", "", "", + /*105 - 109 */ "", "", "", "", "", + /*110 - 114 */ "", "", "", "", "", + /*115 - 119 */ "", "", "", "", "", + /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124"; + + i2c0_pins: i2c0-pins { + pins { + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, + <PINMUX_GPIO55__FUNC_B1_SCL0>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c2_pins: i2c2-pins { + pins { + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, + <PINMUX_GPIO59__FUNC_B1_SCL2>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c3_pins: i2c3-pins { + pins { + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, + <PINMUX_GPIO61__FUNC_B1_SCL3>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c5_pins: i2c5-pins { + pins { + pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, + <PINMUX_GPIO65__FUNC_B1_SCL5>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + i2c6_pins: i2c6-pins { + pins { + pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, + <PINMUX_GPIO67__FUNC_B1_SCL6>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + uart0_pins: uart0-pins { + pins { + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, + <PINMUX_GPIO32__FUNC_I1_URXD0>; + bias-pull-up; + }; + }; + + uart1_pins: uart1-pins { + pins { + pinmux = <PINMUX_GPIO86__FUNC_O_UTXD1>, + <PINMUX_GPIO87__FUNC_I1_URXD1>; + bias-pull-up; + }; + }; + + uart2_pins: uart2-pins { + pins { + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, + <PINMUX_GPIO36__FUNC_I1_URXD2>; + bias-pull-up; + }; + }; + + pcie_pins_default: pcie-default { + mux { + pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, + <PINMUX_GPIO48__FUNC_O_PERSTN>, + <PINMUX_GPIO49__FUNC_B1_CLKREQN>; + bias-pull-up; + }; + }; + + eth_default_pins: eth-default-pins { + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>, + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>, + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>; + drive-strength = <8>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; + drive-strength = <8>; + input-enable; + }; + + pins-power { + pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>, + <PINMUX_GPIO146__FUNC_B_GPIO146>; + output-high; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>; + drive-strength = <8>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; + drive-strength = <8>; + }; + }; + + eth_sleep_pins: eth-sleep-pins { + pins-cc { + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, + <PINMUX_GPIO140__FUNC_B_GPIO140>, + <PINMUX_GPIO141__FUNC_B_GPIO141>, + <PINMUX_GPIO142__FUNC_B_GPIO142>; + }; + + pins-mdio { + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, + <PINMUX_GPIO144__FUNC_B_GPIO144>; + input-disable; + bias-disable; + }; + + pins-rxd { + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, + <PINMUX_GPIO136__FUNC_B_GPIO136>, + <PINMUX_GPIO137__FUNC_B_GPIO137>, + <PINMUX_GPIO138__FUNC_B_GPIO138>; + }; + + pins-txd { + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, + <PINMUX_GPIO132__FUNC_B_GPIO132>, + <PINMUX_GPIO133__FUNC_B_GPIO133>, + <PINMUX_GPIO134__FUNC_B_GPIO134>; + }; + }; + + spi2_pins: spi2-pins { + pins-spi { + pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, + <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, + <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, + <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; + bias-disable; + }; + }; + + audio_default_pins: audio-default-pins { + pins-cmd-dat { + pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK>, + <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>, + <PINMUX_GPIO123__FUNC_O_PCM_DO>, + <PINMUX_GPIO124__FUNC_I0_PCM_DI>; + }; + }; + + usb_default_pins: usb-default-pins { + pins-valid { + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; + input-enable; + }; + }; +}; + +ð { + phy-mode = "rgmii-id"; + phy-handle = <ðernet_phy0>; + snps,reset-active-low; + snps,reset-delays-us = <0 11000 200000>; + mediatek,tx-delay-ps = <30>; + pinctrl-names = "default", "sleep"; + pinctrl-0 = <ð_default_pins>; + pinctrl-1 = <ð_sleep_pins>; + mediatek,mac-wol; + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>; + status = "okay"; +}; + +ð_mdio { + ethernet_phy0: ethernet-phy@3 { + reg = <3>; + compatible = "ethernet-phy-ieee802.3-c22"; + eee-broken-1000t; + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; + }; +}; + +&i2c0 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c0_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c2 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c2_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c3 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c3_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c5 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c5_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&i2c6 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c6_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&uart0 { + pinctrl-0 = <&uart0_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart1 { + pinctrl-0 = <&uart1_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&uart2 { + pinctrl-0 = <&uart2_pins>; + pinctrl-names = "default"; + status = "okay"; +}; + +&pcie { + pinctrl-names = "default"; + pinctrl-0 = <&pcie_pins_default>; + status = "okay"; +}; + +&pciephy { + status = "okay"; +}; + +&spi2 { + pinctrl-0 = <&spi2_pins>; + pinctrl-names = "default"; + mediatek,pad-select = <0>; + #address-cells = <1>; + #size-cells = <0>; + status = "okay"; +}; + +&u3phy0 { + status = "okay"; +}; + +&u3phy1 { + status = "okay"; +}; + +&u3phy2 { + status = "okay"; +}; + +&xhci1 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + + hub_2_0: hub@1 { + compatible = "usb451,8027"; + reg = <1>; + peer-hub = <&hub_3_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <®_fixed_3v3>; + }; + + hub_3_0: hub@2 { + compatible = "usb451,8025"; + reg = <2>; + peer-hub = <&hub_2_0>; + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; + vdd-supply = <®_fixed_3v3>; + }; +}; + +&xhci2 { + status = "okay"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + #address-cells = <1>; + #size-cells = <0>; + + hub@1 { + compatible = "microchip,usb2513bi"; + reg = <1>; + vdd-supply = <®_fixed_3v3>; + }; +}; + +&ssusb0 { + status = "okay"; + dr_mode = "peripheral"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + pinctrl-0 = <&usb_default_pins>; + pinctrl-names = "default"; +}; + +&ssusb1 { + status = "okay"; + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + maximum-speed = "super-speed"; +}; + +&ssusb2 { + status = "okay"; + dr_mode = "host"; + vusb33-supply = <&mt6359_vusb_ldo_reg>; + maximum-speed = "high-speed"; +}; + +&scp_cluster { + status = "okay"; +}; + +&scp_c0 { + firmware-name = "mediatek/mt8188/scp.img"; + memory-region = <&scp_mem>; + status = "okay"; +}; + +&gpu { + mali-supply = <&mt6359_vproc2_buck_reg>; + status = "okay"; +}; + +&adsp { + memory-region = <&adsp_dma_mem>, <&adsp_mem>; + status = "okay"; +}; + +&afe { + memory-region = <&afe_dma_mem>; + status = "okay"; +}; + +&sound { + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; + model = "mt8390-evk"; + pinctrl-names = "default"; + pinctrl-0 = <&audio_default_pins>; + audio-routing = + "Headphone", "Headphone L", + "Headphone", "Headphone R", + "AP DMIC", "AUDGLB", + "AP DMIC", "MIC_BIAS_0", + "AP DMIC", "MIC_BIAS_2", + "DMIC_INPUT", "AP DMIC"; + + mediatek,adsp = <&adsp>; + status = "okay"; +}; diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi new file mode 100644 index 000000000000..d88481beff9d --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi @@ -0,0 +1,209 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Mateusz Koza <mateusz.koza@grinn-global.com> + */ + +#include "mt6359.dtsi" +#include <dt-bindings/input/input.h> + +/ { + aliases { + i2c1 = &i2c1; + mmc0 = &mmc0; + }; +}; + +&i2c1 { + pinctrl-names = "default"; + pinctrl-0 = <&i2c1_pins>; + clock-frequency = <400000>; + status = "okay"; +}; + +&mfg0 { + domain-supply = <&mt6359_vproc2_buck_reg>; +}; + +&mfg1 { + domain-supply = <&mt6359_vsram_others_ldo_reg>; +}; + +&mmc0 { + status = "okay"; + pinctrl-names = "default", "state_uhs"; + pinctrl-0 = <&mmc0_default_pins>; + pinctrl-1 = <&mmc0_uhs_pins>; + bus-width = <8>; + max-frequency = <200000000>; + cap-mmc-highspeed; + mmc-hs200-1_8v; + mmc-hs400-1_8v; + supports-cqe; + cap-mmc-hw-reset; + no-sdio; + no-sd; + hs400-ds-delay = <0x1481b>; + vmmc-supply = <&mt6359_vemc_1_ldo_reg>; + vqmmc-supply = <&mt6359_vufs_ldo_reg>; + non-removable; +}; + +&mt6359_vbbck_ldo_reg { + regulator-always-on; +}; + +&mt6359_vcn18_ldo_reg { + regulator-name = "vcn18_pmu"; + regulator-always-on; +}; + +&mt6359_vcn33_2_bt_ldo_reg { + regulator-name = "vcn33_2_pmu"; + regulator-always-on; +}; + +&mt6359_vcore_buck_reg { + regulator-name = "dvdd_proc_l"; + regulator-always-on; +}; + +&mt6359_vgpu11_buck_reg { + regulator-name = "dvdd_core"; + regulator-always-on; +}; + +&mt6359_vpa_buck_reg { + regulator-name = "vpa_pmu"; + regulator-max-microvolt = <3100000>; +}; + +&mt6359_vproc2_buck_reg { + /* The name "vgpu" is required by mtk-regulator-coupler */ + regulator-name = "vgpu"; + regulator-min-microvolt = <550000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vsram_others_ldo_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vpu_buck_reg { + regulator-name = "dvdd_adsp"; + regulator-always-on; +}; + +&mt6359_vrf12_ldo_reg { + regulator-name = "va12_abb2_pmu"; + regulator-always-on; +}; + +&mt6359_vsim1_ldo_reg { + regulator-name = "vsim1_pmu"; + regulator-enable-ramp-delay = <480>; +}; + +&mt6359_vsram_others_ldo_reg { + /* The name "vsram_gpu" is required by mtk-regulator-coupler */ + regulator-name = "vsram_gpu"; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <800000>; + regulator-coupled-with = <&mt6359_vproc2_buck_reg>; + regulator-coupled-max-spread = <6250>; +}; + +&mt6359_vufs_ldo_reg { + regulator-name = "vufs18_pmu"; + regulator-always-on; +}; + +&pio { + + i2c1_pins: i2c1-pins { + pins { + pinmux = <PINMUX_GPIO58__FUNC_B1_SDA1>, + <PINMUX_GPIO57__FUNC_B1_SCL1>; + bias-pull-up = <MTK_PULL_SET_RSEL_011>; + drive-strength-microamp = <1000>; + }; + }; + + mmc0_default_pins: mmc0-default-pins { + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <6>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <6>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; + + mmc0_uhs_pins: mmc0-uhs-pins { + pins-clk { + pinmux = <PINMUX_GPIO157__FUNC_B1_MSDC0_CLK>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-cmd-dat { + pinmux = <PINMUX_GPIO161__FUNC_B1_MSDC0_DAT0>, + <PINMUX_GPIO160__FUNC_B1_MSDC0_DAT1>, + <PINMUX_GPIO159__FUNC_B1_MSDC0_DAT2>, + <PINMUX_GPIO158__FUNC_B1_MSDC0_DAT3>, + <PINMUX_GPIO154__FUNC_B1_MSDC0_DAT4>, + <PINMUX_GPIO153__FUNC_B1_MSDC0_DAT5>, + <PINMUX_GPIO152__FUNC_B1_MSDC0_DAT6>, + <PINMUX_GPIO151__FUNC_B1_MSDC0_DAT7>, + <PINMUX_GPIO156__FUNC_B1_MSDC0_CMD>; + input-enable; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + + pins-ds { + pinmux = <PINMUX_GPIO162__FUNC_B0_MSDC0_DSL>; + drive-strength = <8>; + bias-pull-down = <MTK_PUPD_SET_R1R0_10>; + }; + + pins-rst { + pinmux = <PINMUX_GPIO155__FUNC_O_MSDC0_RSTB>; + drive-strength = <8>; + bias-pull-up = <MTK_PUPD_SET_R1R0_01>; + }; + }; +}; + +&pmic { + interrupt-parent = <&pio>; + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; + + mt6359keys: keys { + compatible = "mediatek,mt6359-keys"; + mediatek,long-press-mode = <1>; + power-off-time-sec = <0>; + + power-key { + linux,keycodes = <KEY_POWER>; + wakeup-source; + }; + }; +}; -- 2.43.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 2025-09-08 13:05 ` [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Mateusz Koza @ 2025-09-09 8:19 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 10+ messages in thread From: AngeloGioacchino Del Regno @ 2025-09-09 8:19 UTC (permalink / raw) To: Mateusz Koza, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, andrew Il 08/09/25 15:05, Mateusz Koza ha scritto: > Add support for Grinn GenioSBC-700. The Grinn GenioSBC-700 is a > single-board computer based on the MediaTek Genio 700 SoC. Its device > tree is split into separate SoM (.dtsi) and SBC (.dtsi) files, which are > combined in the SoC-specific .dts file. > > More details about the hardware: > - https://grinn-global.com/products/grinn-geniosom-700 > - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc > > Reviewed-by: Andrew Lunn <andrew@lunn.ch> > Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > .../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 + > .../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 538 ++++++++++++++++++ > .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 +++++++ > 4 files changed, 767 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi > create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index a4df4c21399e..b37a8c65e724 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -101,6 +101,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-kontron-3-5-sbc-i1200.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-radxa-nio-12l-8-hd-panel.dtbo > diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts > new file mode 100644 > index 000000000000..a37507a5a5d0 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2025 Grinn sp. z o.o. > + * Author: Mateusz Koza <mateusz.koza@grinn-global.com> > + */ > +/dts-v1/; > + > +#include "mt8188.dtsi" > +#include "mt8390-grinn-genio-som.dtsi" > +#include "mt8390-grinn-genio-sbc.dtsi" > + > +/ { > + model = "Grinn GenioSBC-700"; > + compatible = "grinn,genio-700-sbc", "mediatek,mt8390", "mediatek,mt8188"; Just a nit: please leave one blank line here. > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 1 0x00000000>; > + }; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi > new file mode 100644 > index 000000000000..0e6006cd8ed9 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi > @@ -0,0 +1,538 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2025 Grinn sp. z o.o. > + * Author: Mateusz Koza <mateusz.koza@grinn-global.com> > + */ > + > +#include <dt-bindings/gpio/gpio.h> > + > +/ { > + chassis-type = "embedded"; > + aliases { > + ethernet0 = ð > + i2c0 = &i2c0; > + i2c2 = &i2c2; > + i2c3 = &i2c3; > + i2c5 = &i2c5; > + i2c6 = &i2c6; > + serial0 = &uart0; > + }; > + Please move chassis-type here. > + chosen { > + stdout-path = "serial0:921600n8"; > + }; > + > + firmware { > + optee { > + compatible = "linaro,optee-tz"; > + method = "smc"; > + }; > + }; > + > + reserved-memory { > + #address-cells = <2>; > + #size-cells = <2>; > + ranges; > + > + /* > + * 12 MiB reserved for OP-TEE (BL32) > + * +-----------------------+ 0x43e0_0000 > + * | SHMEM 2MiB | > + * +-----------------------+ 0x43c0_0000 > + * | | TA_RAM 8MiB | > + * + TZDRAM +--------------+ 0x4340_0000 > + * | | TEE_RAM 2MiB | > + * +-----------------------+ 0x4320_0000 > + */ > + optee_reserved: optee@43200000 { > + no-map; > + reg = <0 0x43200000 0 0x00c00000>; > + }; > + > + scp_mem: memory@50000000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x50000000 0 0x2900000>; > + no-map; > + }; > + > + /* 2 MiB reserved for ARM Trusted Firmware (BL31) */ > + bl31_secmon_reserved: memory@54600000 { > + no-map; > + reg = <0 0x54600000 0x0 0x200000>; > + }; > + > + apu_mem: memory@55000000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x55000000 0 0x1400000>; /* 20 MB */ > + }; > + > + vpu_mem: memory@57000000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x57000000 0 0x1400000>; /* 20 MB */ > + }; > + > + adsp_mem: memory@60000000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x60000000 0 0xf00000>; > + no-map; > + }; > + > + afe_dma_mem: memory@60f00000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x60f00000 0 0x100000>; > + no-map; > + }; > + > + adsp_dma_mem: memory@61000000 { > + compatible = "shared-dma-pool"; > + reg = <0 0x61000000 0 0x100000>; > + no-map; > + }; > + }; > + > + reg_sbc_vsys: regulator-vsys { > + compatible = "regulator-fixed"; > + regulator-name = "vsys"; > + regulator-always-on; > + regulator-boot-on; > + }; > + > + reg_fixed_5v: regulator-0 { > + compatible = "regulator-fixed"; > + regulator-name = "fixed_5v"; Can we please avoid underscores? regulator-name = "fixed-5v0"; > + regulator-min-microvolt = <5000000>; > + regulator-max-microvolt = <5000000>; > + enable-active-high; > + regulator-always-on; > + vin-supply = <®_sbc_vsys>; > + }; > + > + reg_fixed_4v2: regulator-1 { > + compatible = "regulator-fixed"; > + regulator-name = "fixed_4v2"; fixed-4v2 > + regulator-min-microvolt = <4200000>; > + regulator-max-microvolt = <4200000>; > + enable-active-high; > + regulator-always-on; > + vin-supply = <®_sbc_vsys>; > + }; > + > + reg_fixed_3v3: regulator-2 { > + compatible = "regulator-fixed"; > + regulator-name = "fixed_3v3"; fixed-3v3 > + regulator-min-microvolt = <3300000>; > + regulator-max-microvolt = <3300000>; > + enable-active-high; > + regulator-always-on; > + vin-supply = <®_sbc_vsys>; > + }; > +}; > + > +&pio { > + gpio-line-names = > + /* 0 - 4 */ "RPI_GPIO0", "RPI_GPIO1", "", "", "RPI_GPIO4", > + /* 5 - 9 */ "", "RPI_GPIO6", "", "", "RPI_GPIO9", > + /* 10 - 14 */ "RPI_GPIO10", "RPI_GPIO11", "", "", "", > + /* 15 - 19 */ "", "", "", "", "", > + /* 20 - 24 */ "", "RPI_GPIO21", "", "RPI_GPIO23", "", > + /* 25 - 29 */ "", "", "", "", "", > + /* 30 - 34 */ "RPI_GPIO30", "", "", "", "", > + /* 35 - 39 */ "RPI_GPIO35", "RPI_GPIO36", "", "", "", > + /* 40 - 44 */ "", "", "", "", "", > + /* 45 - 49 */ "", "", "", "", "", > + /* 50 - 54 */ "", "", "", "", "", > + /* 55 - 59 */ "RPI_GPIO55", "RPI_GPIO56", "", "", "RPI_GPIO59", > + /* 60 - 64 */ "RPI_GPIO60", "", "", "", "", > + /* 65 - 69 */ "", "", "", "", "RPI_GPIO69", > + /* 70 - 74 */ "", "", "RPI_GPIO72", "RPI_GPIO73", "RPI_GPIO74", > + /* 75 - 79 */ "", "", "", "", "RPI_GPIO79", > + /* 80 - 84 */ "RPI_GPIO80", "RPI_GPIO81", "RPI_GPIO82", "", "", > + /* 85 - 89 */ "", "", "", "", "", > + /* 90 - 94 */ "", "", "", "", "", > + /* 95 - 99 */ "", "", "", "", "", > + /*100 - 104 */ "", "", "", "", "", > + /*105 - 109 */ "", "", "", "", "", > + /*110 - 114 */ "", "", "", "", "", > + /*115 - 119 */ "", "", "", "", "", > + /*120 - 124 */ "", "RPI_GPIO121", "RPI_GPIO122", "RPI_GPIO123", "RPI_GPIO124"; > + > + i2c0_pins: i2c0-pins { > + pins { > + pinmux = <PINMUX_GPIO56__FUNC_B1_SDA0>, > + <PINMUX_GPIO55__FUNC_B1_SCL0>; > + bias-pull-up = <MTK_PULL_SET_RSEL_011>; > + drive-strength-microamp = <1000>; > + }; > + }; > + > + i2c2_pins: i2c2-pins { > + pins { > + pinmux = <PINMUX_GPIO60__FUNC_B1_SDA2>, > + <PINMUX_GPIO59__FUNC_B1_SCL2>; > + bias-pull-up = <MTK_PULL_SET_RSEL_011>; > + drive-strength-microamp = <1000>; > + }; > + }; > + > + i2c3_pins: i2c3-pins { > + pins { > + pinmux = <PINMUX_GPIO62__FUNC_B1_SDA3>, > + <PINMUX_GPIO61__FUNC_B1_SCL3>; > + bias-pull-up = <MTK_PULL_SET_RSEL_011>; > + drive-strength-microamp = <1000>; > + }; > + }; > + > + i2c5_pins: i2c5-pins { > + pins { > + pinmux = <PINMUX_GPIO66__FUNC_B1_SDA5>, > + <PINMUX_GPIO65__FUNC_B1_SCL5>; > + bias-pull-up = <MTK_PULL_SET_RSEL_011>; > + drive-strength-microamp = <1000>; > + }; > + }; > + > + i2c6_pins: i2c6-pins { > + pins { > + pinmux = <PINMUX_GPIO68__FUNC_B1_SDA6>, > + <PINMUX_GPIO67__FUNC_B1_SCL6>; > + bias-pull-up = <MTK_PULL_SET_RSEL_011>; > + drive-strength-microamp = <1000>; > + }; > + }; > + > + uart0_pins: uart0-pins { > + pins { > + pinmux = <PINMUX_GPIO31__FUNC_O_UTXD0>, > + <PINMUX_GPIO32__FUNC_I1_URXD0>; > + bias-pull-up; > + }; > + }; > + > + uart1_pins: uart1-pins { > + pins { > + pinmux = <PINMUX_GPIO86__FUNC_O_UTXD1>, > + <PINMUX_GPIO87__FUNC_I1_URXD1>; > + bias-pull-up; > + }; > + }; > + > + uart2_pins: uart2-pins { > + pins { > + pinmux = <PINMUX_GPIO35__FUNC_O_UTXD2>, > + <PINMUX_GPIO36__FUNC_I1_URXD2>; > + bias-pull-up; > + }; > + }; > + > + pcie_pins_default: pcie-default { > + mux { > + pinmux = <PINMUX_GPIO47__FUNC_I1_WAKEN>, > + <PINMUX_GPIO48__FUNC_O_PERSTN>, > + <PINMUX_GPIO49__FUNC_B1_CLKREQN>; > + bias-pull-up; > + }; > + }; > + > + eth_default_pins: eth-default-pins { > + pins-cc { > + pinmux = <PINMUX_GPIO139__FUNC_B0_GBE_TXC>, > + <PINMUX_GPIO140__FUNC_I0_GBE_RXC>, > + <PINMUX_GPIO141__FUNC_I0_GBE_RXDV>, > + <PINMUX_GPIO142__FUNC_O_GBE_TXEN>; > + drive-strength = <8>; > + }; > + > + pins-mdio { > + pinmux = <PINMUX_GPIO143__FUNC_O_GBE_MDC>, > + <PINMUX_GPIO144__FUNC_B1_GBE_MDIO>; > + drive-strength = <8>; > + input-enable; > + }; > + > + pins-power { > + pinmux = <PINMUX_GPIO145__FUNC_B_GPIO145>, > + <PINMUX_GPIO146__FUNC_B_GPIO146>; > + output-high; > + }; > + > + pins-rxd { > + pinmux = <PINMUX_GPIO135__FUNC_I0_GBE_RXD3>, > + <PINMUX_GPIO136__FUNC_I0_GBE_RXD2>, > + <PINMUX_GPIO137__FUNC_I0_GBE_RXD1>, > + <PINMUX_GPIO138__FUNC_I0_GBE_RXD0>; > + drive-strength = <8>; > + }; > + > + pins-txd { > + pinmux = <PINMUX_GPIO131__FUNC_O_GBE_TXD3>, > + <PINMUX_GPIO132__FUNC_O_GBE_TXD2>, > + <PINMUX_GPIO133__FUNC_O_GBE_TXD1>, > + <PINMUX_GPIO134__FUNC_O_GBE_TXD0>; > + drive-strength = <8>; > + }; > + }; > + > + eth_sleep_pins: eth-sleep-pins { > + pins-cc { > + pinmux = <PINMUX_GPIO139__FUNC_B_GPIO139>, > + <PINMUX_GPIO140__FUNC_B_GPIO140>, > + <PINMUX_GPIO141__FUNC_B_GPIO141>, > + <PINMUX_GPIO142__FUNC_B_GPIO142>; > + }; > + > + pins-mdio { > + pinmux = <PINMUX_GPIO143__FUNC_B_GPIO143>, > + <PINMUX_GPIO144__FUNC_B_GPIO144>; > + input-disable; > + bias-disable; > + }; > + > + pins-rxd { > + pinmux = <PINMUX_GPIO135__FUNC_B_GPIO135>, > + <PINMUX_GPIO136__FUNC_B_GPIO136>, > + <PINMUX_GPIO137__FUNC_B_GPIO137>, > + <PINMUX_GPIO138__FUNC_B_GPIO138>; > + }; > + > + pins-txd { > + pinmux = <PINMUX_GPIO131__FUNC_B_GPIO131>, > + <PINMUX_GPIO132__FUNC_B_GPIO132>, > + <PINMUX_GPIO133__FUNC_B_GPIO133>, > + <PINMUX_GPIO134__FUNC_B_GPIO134>; > + }; > + }; > + > + spi2_pins: spi2-pins { > + pins-spi { > + pinmux = <PINMUX_GPIO79__FUNC_O_SPIM2_CSB>, > + <PINMUX_GPIO80__FUNC_O_SPIM2_CLK>, > + <PINMUX_GPIO81__FUNC_B0_SPIM2_MOSI>, > + <PINMUX_GPIO82__FUNC_B0_SPIM2_MISO>; > + bias-disable; > + }; > + }; > + > + audio_default_pins: audio-default-pins { > + pins-cmd-dat { > + pinmux = <PINMUX_GPIO121__FUNC_B0_PCM_CLK>, > + <PINMUX_GPIO122__FUNC_B0_PCM_SYNC>, > + <PINMUX_GPIO123__FUNC_O_PCM_DO>, > + <PINMUX_GPIO124__FUNC_I0_PCM_DI>; > + }; > + }; > + > + usb_default_pins: usb-default-pins { > + pins-valid { > + pinmux = <PINMUX_GPIO85__FUNC_I0_VBUSVALID>; > + input-enable; > + }; > + }; > +}; > + > +ð { Please reorder the nodes per type (generic first, vendor specific last) and alphabetically, like so: > + phy-mode = "rgmii-id"; > + phy-handle = <ðernet_phy0>; pinctrl-names pinctrl-0 pinctrl-1 mediatek,..... snps,..... status = "okay"; > + snps,reset-active-low; > + snps,reset-delays-us = <0 11000 200000>; > + mediatek,tx-delay-ps = <30>; > + pinctrl-names = "default", "sleep"; > + pinctrl-0 = <ð_default_pins>; > + pinctrl-1 = <ð_sleep_pins>; > + mediatek,mac-wol; > + snps,reset-gpio = <&pio 147 GPIO_ACTIVE_LOW>; > + status = "okay"; > +}; > + > +ð_mdio { > + ethernet_phy0: ethernet-phy@3 { compatible reg interrupts-extended eee-broken-1000t; > + reg = <3>; > + compatible = "ethernet-phy-ieee802.3-c22"; > + eee-broken-1000t; > + interrupts-extended = <&pio 148 IRQ_TYPE_LEVEL_LOW>; > + }; > +}; > + > +&xhci1 { #address-cells #size-cells vusb33-supply status = "okay" subnodes > + status = "okay"; > + vusb33-supply = <&mt6359_vusb_ldo_reg>; > + #address-cells = <1>; > + #size-cells = <0>; > + > + hub_2_0: hub@1 { > + compatible = "usb451,8027"; > + reg = <1>; > + peer-hub = <&hub_3_0>; > + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; > + vdd-supply = <®_fixed_3v3>; > + }; > + > + hub_3_0: hub@2 { > + compatible = "usb451,8025"; > + reg = <2>; > + peer-hub = <&hub_2_0>; > + reset-gpios = <&pio 7 GPIO_ACTIVE_HIGH>; > + vdd-supply = <®_fixed_3v3>; > + }; > +}; > + > +&xhci2 { > + status = "okay"; > + vusb33-supply = <&mt6359_vusb_ldo_reg>; > + #address-cells = <1>; > + #size-cells = <0>; same here > + > + hub@1 { > + compatible = "microchip,usb2513bi"; > + reg = <1>; > + vdd-supply = <®_fixed_3v3>; > + }; > +}; > + > +&ssusb0 { > + status = "okay"; > + dr_mode = "peripheral"; > + vusb33-supply = <&mt6359_vusb_ldo_reg>; > + pinctrl-0 = <&usb_default_pins>; > + pinctrl-names = "default"; dr_mode pinctrl vusb status > +}; > + > +&ssusb1 { > + status = "okay"; > + dr_mode = "host"; > + vusb33-supply = <&mt6359_vusb_ldo_reg>; > + maximum-speed = "super-speed"; dr_mode maximum-speed vusb status > +}; > + > +&ssusb2 { > + status = "okay"; > + dr_mode = "host"; > + vusb33-supply = <&mt6359_vusb_ldo_reg>; > + maximum-speed = "high-speed"; same here > +}; > + > +&scp_cluster { > + status = "okay"; > +}; > + > +&scp_c0 { > + firmware-name = "mediatek/mt8188/scp.img"; please drop firmware-name, unfortunately this is not acceptable upstream. > + memory-region = <&scp_mem>; > + status = "okay"; > +}; > + > +&gpu { > + mali-supply = <&mt6359_vproc2_buck_reg>; > + status = "okay"; > +}; > + > +&adsp { > + memory-region = <&adsp_dma_mem>, <&adsp_mem>; > + status = "okay"; > +}; > + > +&afe { > + memory-region = <&afe_dma_mem>; > + status = "okay"; > +}; > + > +&sound { > + compatible = "mediatek,mt8390-mt6359-evk", "mediatek,mt8188-mt6359-evb"; > + model = "mt8390-evk"; > + pinctrl-names = "default"; > + pinctrl-0 = <&audio_default_pins>; > + audio-routing = > + "Headphone", "Headphone L", > + "Headphone", "Headphone R", > + "AP DMIC", "AUDGLB", > + "AP DMIC", "MIC_BIAS_0", > + "AP DMIC", "MIC_BIAS_2", > + "DMIC_INPUT", "AP DMIC"; > + > + mediatek,adsp = <&adsp>; > + status = "okay"; > +}; > diff --git a/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi > new file mode 100644 > index 000000000000..d88481beff9d > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi > @@ -0,0 +1,209 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2025 Grinn sp. z o.o. > + * Author: Mateusz Koza <mateusz.koza@grinn-global.com> > + */ > + > +#include "mt6359.dtsi" > +#include <dt-bindings/input/input.h> > + > +/ { > + aliases { > + i2c1 = &i2c1; > + mmc0 = &mmc0; > + }; > +}; > + ..snip.. > + > +&pmic { > + interrupt-parent = <&pio>; > + interrupts = <222 IRQ_TYPE_LEVEL_HIGH>; interrupts-extended = <&pio 222 IRQ_TYPE_LEVEL_HIGH>; > + > + mt6359keys: keys { (drop handle) keys { > + compatible = "mediatek,mt6359-keys"; > + mediatek,long-press-mode = <1>; > + power-off-time-sec = <0>; > + > + power-key { > + linux,keycodes = <KEY_POWER>; > + wakeup-source; > + }; > + }; > +}; Cheers, Angelo ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc 2025-09-08 13:05 [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Mateusz Koza 2025-09-08 13:05 ` [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Mateusz Koza @ 2025-09-08 13:05 ` Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-08 13:05 ` [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 Mateusz Koza ` (2 subsequent siblings) 4 siblings, 1 reply; 10+ messages in thread From: Mateusz Koza @ 2025-09-08 13:05 UTC (permalink / raw) To: angelogioacchino.delregno, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, mateusz.koza, andrew, Conor Dooley Add device tree bindings support for the Grinn GenioSBC-700, a single-board computer based on the MediaTek Genio 700 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-700 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 19ed9448c9c2..448241939a75 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -436,6 +436,7 @@ properties: - const: mediatek,mt8188 - items: - enum: + - grinn,genio-700-sbc - mediatek,mt8390-evk - const: mediatek,mt8390 - const: mediatek,mt8188 -- 2.43.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc 2025-09-08 13:05 ` [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Mateusz Koza @ 2025-09-09 8:19 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 10+ messages in thread From: AngeloGioacchino Del Regno @ 2025-09-09 8:19 UTC (permalink / raw) To: Mateusz Koza, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, andrew, Conor Dooley Il 08/09/25 15:05, Mateusz Koza ha scritto: > Add device tree bindings support for the Grinn GenioSBC-700, a > single-board computer based on the MediaTek Genio 700 SoC. > > More details about the hardware: > - https://grinn-global.com/products/grinn-geniosom-700 > - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 2025-09-08 13:05 [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Mateusz Koza 2025-09-08 13:05 ` [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Mateusz Koza 2025-09-08 13:05 ` [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Mateusz Koza @ 2025-09-08 13:05 ` Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-08 13:05 ` [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Mateusz Koza 2025-09-10 9:52 ` [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Matthias Brugger 4 siblings, 1 reply; 10+ messages in thread From: Mateusz Koza @ 2025-09-08 13:05 UTC (permalink / raw) To: angelogioacchino.delregno, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, mateusz.koza, andrew From: Bartosz Bilas <b.bilas@grinn-global.com> Add support for Grinn GenioSBC-510. Based on the commit introducing support for the Grinn GenioSBC-700, this change adds support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com> --- arch/arm64/boot/dts/mediatek/Makefile | 1 + .../mediatek/mt8370-grinn-genio-510-sbc.dts | 19 +++++++++++++++++++ 2 files changed, 20 insertions(+) create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile index b37a8c65e724..4b8ee6970f40 100644 --- a/arch/arm64/boot/dts/mediatek/Makefile +++ b/arch/arm64/boot/dts/mediatek/Makefile @@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb diff --git a/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts new file mode 100644 index 000000000000..117ea694cda3 --- /dev/null +++ b/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts @@ -0,0 +1,19 @@ +// SPDX-License-Identifier: (GPL-2.0 OR MIT) +/* + * Copyright (C) 2025 Grinn sp. z o.o. + * Author: Bartosz Bilas <bartosz.bilas@grinn-global.com> + */ +/dts-v1/; + +#include "mt8370.dtsi" +#include "mt8390-grinn-genio-som.dtsi" +#include "mt8390-grinn-genio-sbc.dtsi" + +/ { + model = "Grinn GenioSBC-510"; + compatible = "grinn,genio-510-sbc", "mediatek,mt8370", "mediatek,mt8188"; + memory@40000000 { + device_type = "memory"; + reg = <0 0x40000000 1 0x00000000>; + }; +}; -- 2.43.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 2025-09-08 13:05 ` [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 Mateusz Koza @ 2025-09-09 8:19 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 10+ messages in thread From: AngeloGioacchino Del Regno @ 2025-09-09 8:19 UTC (permalink / raw) To: Mateusz Koza, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, andrew Il 08/09/25 15:05, Mateusz Koza ha scritto: > From: Bartosz Bilas <b.bilas@grinn-global.com> > > Add support for Grinn GenioSBC-510. Based on the commit introducing > support for the Grinn GenioSBC-700, this change adds support for the > Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio > 510 SoC. > > More details about the hardware: > - https://grinn-global.com/products/grinn-geniosom-510 > - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc > > Signed-off-by: Bartosz Bilas <b.bilas@grinn-global.com> > --- > arch/arm64/boot/dts/mediatek/Makefile | 1 + > .../mediatek/mt8370-grinn-genio-510-sbc.dts | 19 +++++++++++++++++++ > 2 files changed, 20 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts > > diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile > index b37a8c65e724..4b8ee6970f40 100644 > --- a/arch/arm64/boot/dts/mediatek/Makefile > +++ b/arch/arm64/boot/dts/mediatek/Makefile > @@ -99,6 +99,7 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-demo.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8365-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-genio-510-evk.dtb > +dtb-$(CONFIG_ARCH_MEDIATEK) += mt8370-grinn-genio-510-sbc.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8395-genio-1200-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-genio-700-evk.dtb > dtb-$(CONFIG_ARCH_MEDIATEK) += mt8390-grinn-genio-700-sbc.dtb > diff --git a/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts b/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts > new file mode 100644 > index 000000000000..117ea694cda3 > --- /dev/null > +++ b/arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts > @@ -0,0 +1,19 @@ > +// SPDX-License-Identifier: (GPL-2.0 OR MIT) > +/* > + * Copyright (C) 2025 Grinn sp. z o.o. > + * Author: Bartosz Bilas <bartosz.bilas@grinn-global.com> > + */ > +/dts-v1/; > + > +#include "mt8370.dtsi" > +#include "mt8390-grinn-genio-som.dtsi" > +#include "mt8390-grinn-genio-sbc.dtsi" > + > +/ { > + model = "Grinn GenioSBC-510"; > + compatible = "grinn,genio-510-sbc", "mediatek,mt8370", "mediatek,mt8188"; only because you have to anyway send a v5.... blank line here please after which Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> > + memory@40000000 { > + device_type = "memory"; > + reg = <0 0x40000000 1 0x00000000>; > + }; > +}; ^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc 2025-09-08 13:05 [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Mateusz Koza ` (2 preceding siblings ...) 2025-09-08 13:05 ` [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 Mateusz Koza @ 2025-09-08 13:05 ` Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-10 9:52 ` [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Matthias Brugger 4 siblings, 1 reply; 10+ messages in thread From: Mateusz Koza @ 2025-09-08 13:05 UTC (permalink / raw) To: angelogioacchino.delregno, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, mateusz.koza, andrew, Conor Dooley Add device tree bindings support for the Grinn GenioSBC-510, a single-board computer based on the MediaTek Genio 510 SoC. More details about the hardware: - https://grinn-global.com/products/grinn-geniosom-510 - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc Acked-by: Conor Dooley <conor.dooley@microchip.com> Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> --- Documentation/devicetree/bindings/arm/mediatek.yaml | 1 + 1 file changed, 1 insertion(+) diff --git a/Documentation/devicetree/bindings/arm/mediatek.yaml b/Documentation/devicetree/bindings/arm/mediatek.yaml index 448241939a75..f04277873694 100644 --- a/Documentation/devicetree/bindings/arm/mediatek.yaml +++ b/Documentation/devicetree/bindings/arm/mediatek.yaml @@ -431,6 +431,7 @@ properties: - const: mediatek,mt8365 - items: - enum: + - grinn,genio-510-sbc - mediatek,mt8370-evk - const: mediatek,mt8370 - const: mediatek,mt8188 -- 2.43.0 ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc 2025-09-08 13:05 ` [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Mateusz Koza @ 2025-09-09 8:19 ` AngeloGioacchino Del Regno 0 siblings, 0 replies; 10+ messages in thread From: AngeloGioacchino Del Regno @ 2025-09-09 8:19 UTC (permalink / raw) To: Mateusz Koza, robh Cc: krzk+dt, conor+dt, matthias.bgg, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, andrew, Conor Dooley Il 08/09/25 15:05, Mateusz Koza ha scritto: > Add device tree bindings support for the Grinn GenioSBC-510, a > single-board computer based on the MediaTek Genio 510 SoC. > > More details about the hardware: > - https://grinn-global.com/products/grinn-geniosom-510 > - https://grinn-global.com/products/grinn-genioboard-edge-ai-sbc > > Acked-by: Conor Dooley <conor.dooley@microchip.com> > Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com> ^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards 2025-09-08 13:05 [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Mateusz Koza ` (3 preceding siblings ...) 2025-09-08 13:05 ` [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Mateusz Koza @ 2025-09-10 9:52 ` Matthias Brugger 4 siblings, 0 replies; 10+ messages in thread From: Matthias Brugger @ 2025-09-10 9:52 UTC (permalink / raw) To: Mateusz Koza, angelogioacchino.delregno, robh Cc: krzk+dt, conor+dt, linux-kernel, linux-arm-kernel, linux-mediatek, devicetree, marcin.czarnecki, b.bilas, andrew Patch 2 and 4 queued, thanks Matthias On 08/09/2025 15:05, Mateusz Koza wrote: > This patch series adds support for Grinn GenioSBC-510 and GenioSBC-700 > boards based on MediaTek MT8370 and MT8390 SoCs, respectively. It > includes device tree files for both boards, updates to the device tree > bindings, and necessary modifications to the Makefile. > > As far as I know, <angelogioacchino.delregno@collabora.com> has access > to the schematics for these boards, as we've shared them under NDA with > Collabora. > > Signed-off-by: Mateusz Koza <mateusz.koza@grinn-global.com> > --- > v2: Fixed the subject prefixes, > Fixed alignment in dts files, > Added missing SPDX-License-Identifier, > Fixed the ordering in dt-bindings, > Dropped redundant info from commit messages, > Run checkpatch.pl on the patchset and fixed the issues, > as suggested by Krzysztof Kozlowski <krzk@kernel.org>. > > v3: Changed eth phy-mode to 'rgmii-id', > Changed eth mediatek,tx-delay-ps to 30, > as suggested by Andrew Lunn <andrew@lunn.ch>. > > v4: Removed the nodes that are not present in upstream, > as suggested by Louis-Alexis <angelogioacchino.delregno@collabora.com>. > > Added default pinctrl to ssusb0, > Enabled the scp_cluster node, > as suggested by Bartosz Biłas <b.bilas@grinn-global.com>. > --- > > Bartosz Bilas (1): > arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn > GenioSBC-510 > > Mateusz Koza (3): > arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 > dt-bindings: arm: mediatek: Add grinn,genio-700-sbc > dt-bindings: arm: mediatek: Add grinn,genio-510-sbc > > .../devicetree/bindings/arm/mediatek.yaml | 2 + > arch/arm64/boot/dts/mediatek/Makefile | 2 + > .../mediatek/mt8370-grinn-genio-510-sbc.dts | 19 + > .../mediatek/mt8390-grinn-genio-700-sbc.dts | 19 + > .../dts/mediatek/mt8390-grinn-genio-sbc.dtsi | 538 ++++++++++++++++++ > .../dts/mediatek/mt8390-grinn-genio-som.dtsi | 209 +++++++ > 6 files changed, 789 insertions(+) > create mode 100644 arch/arm64/boot/dts/mediatek/mt8370-grinn-genio-510-sbc.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-700-sbc.dts > create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-sbc.dtsi > create mode 100644 arch/arm64/boot/dts/mediatek/mt8390-grinn-genio-som.dtsi > ^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2025-09-10 9:52 UTC | newest] Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-09-08 13:05 [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Mateusz Koza 2025-09-08 13:05 ` [PATCH v4 1/4] arm64: dts: mediatek: mt8390-genio-700-evk: Add Grinn GenioSBC-700 Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-08 13:05 ` [PATCH v4 2/4] dt-bindings: arm: mediatek: Add grinn,genio-700-sbc Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-08 13:05 ` [PATCH v4 3/4] arm64: dts: mediatek: mt8370-grinn-genio-510-sbc: Add Grinn GenioSBC-510 Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-08 13:05 ` [PATCH v4 4/4] dt-bindings: arm: mediatek: Add grinn,genio-510-sbc Mateusz Koza 2025-09-09 8:19 ` AngeloGioacchino Del Regno 2025-09-10 9:52 ` [PATCH v4 0/4] Add support for Grinn GenioSBC-510/700 boards Matthias Brugger
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