[PATCH v3 0/3] dpum clock support for Exynos Auto v9 SoC

[PATCH v3 0/3] dpum clock support for Exynos Auto v9 SoC

[Kwanghoon Son]

DPUM (Display Processing Unit Main) is main dpu for Exynosautov9.
    
This patches enable clock for dpum, sysmmu(iommu).

I tested using sysmmu, DPP, DECON, DP on sdk board (modetest works).

Signed-off-by: Kwanghoon Son <k.son@samsung.com>
---
Changes in v3:
- Rename clock-names dout_clkcmu_dpum_bus to bus

Changes in v2:
- Squash patch 1,2 to make headers with schema.

---
Kwanghoon Son (3):
      dt-bindings: clock: exynosautov9: add dpum clock
      arm64: dts: exynosautov9: add dpum clock DT nodes
      clk: samsung: exynosautov9: add dpum clock support

 .../bindings/clock/samsung,exynosautov9-clock.yaml | 19 +++++
 arch/arm64/boot/dts/exynos/exynosautov9.dtsi       | 10 +++
 drivers/clk/samsung/clk-exynosautov9.c             | 83 ++++++++++++++++++++++
 include/dt-bindings/clock/samsung,exynosautov9.h   | 11 +++
 4 files changed, 123 insertions(+)
---
base-commit: de9c2c66ad8e787abec7c9d7eff4f8c3cdd28aed
change-id: 20240809-clk_dpum-66a8b28fd7f4

Best regards,
-- 
Kwanghoon Son <k.son@samsung.com>

[PATCH v3 1/3] dt-bindings: clock: exynosautov9: add dpum clock

[Kwanghoon Son]

Add dpum clock definitions and compatibles.

Also used clock name 'bus' instead of full clock name
dout_clkcmu_dpum_bus like other board cmu schema (GS101).

Signed-off-by: Kwanghoon Son <k.son@samsung.com>
---
 .../bindings/clock/samsung,exynosautov9-clock.yaml    | 19 +++++++++++++++++++
 include/dt-bindings/clock/samsung,exynosautov9.h      | 11 +++++++++++
 2 files changed, 30 insertions(+)

diff --git a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
index 55c4f94a14d1..32f39e543b36 100644
--- a/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
+++ b/Documentation/devicetree/bindings/clock/samsung,exynosautov9-clock.yaml
@@ -35,6 +35,7 @@ properties:
       - samsung,exynosautov9-cmu-top
       - samsung,exynosautov9-cmu-busmc
       - samsung,exynosautov9-cmu-core
+      - samsung,exynosautov9-cmu-dpum
       - samsung,exynosautov9-cmu-fsys0
       - samsung,exynosautov9-cmu-fsys1
       - samsung,exynosautov9-cmu-fsys2
@@ -109,6 +110,24 @@ allOf:
             - const: oscclk
             - const: dout_clkcmu_core_bus
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            const: samsung,exynosautov9-cmu-dpum
+
+    then:
+      properties:
+        clocks:
+          items:
+            - description: External reference clock (26 MHz)
+            - description: DPU Main bus clock (from CMU_TOP)
+
+        clock-names:
+          items:
+            - const: oscclk
+            - const: bus
+
   - if:
       properties:
         compatible:
diff --git a/include/dt-bindings/clock/samsung,exynosautov9.h b/include/dt-bindings/clock/samsung,exynosautov9.h
index 3065375c2d8b..ce8fb8f7d718 100644
--- a/include/dt-bindings/clock/samsung,exynosautov9.h
+++ b/include/dt-bindings/clock/samsung,exynosautov9.h
@@ -179,6 +179,17 @@
 #define CLK_GOUT_CORE_CCI_PCLK		4
 #define CLK_GOUT_CORE_CMU_CORE_PCLK	5
 
+/* CMU_DPUM */
+#define CLK_MOUT_DPUM_BUS_USER		1
+#define CLK_DOUT_DPUM_BUSP		2
+#define CLK_GOUT_DPUM_ACLK_DECON	3
+#define CLK_GOUT_DPUM_ACLK_DMA		4
+#define CLK_GOUT_DPUM_ACLK_DPP		5
+#define CLK_GOUT_DPUM_SYSMMU_D0_CLK	6
+#define CLK_GOUT_DPUM_SYSMMU_D1_CLK	7
+#define CLK_GOUT_DPUM_SYSMMU_D2_CLK	8
+#define CLK_GOUT_DPUM_SYSMMU_D3_CLK	9
+
 /* CMU_FSYS0 */
 #define CLK_MOUT_FSYS0_BUS_USER		1
 #define CLK_MOUT_FSYS0_PCIE_USER	2

-- 
2.39.2

[PATCH v3 2/3] arm64: dts: exynosautov9: add dpum clock DT nodes

[Kwanghoon Son]

Add dpum clock for sysmmu, dpu.

Signed-off-by: Kwanghoon Son <k.son@samsung.com>
---
 arch/arm64/boot/dts/exynos/exynosautov9.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)

diff --git a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
index 0248329da49a..599e72824875 100644
--- a/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
+++ b/arch/arm64/boot/dts/exynos/exynosautov9.dtsi
@@ -251,6 +251,16 @@ cmu_fsys2: clock-controller@17c00000 {
 				      "dout_fsys2_clkcmu_ethernet";
 		};
 
+		cmu_dpum: clock-controller@18c00000 {
+			compatible = "samsung,exynosautov9-cmu-dpum";
+			reg = <0x18c00000 0x8000>;
+			#clock-cells = <1>;
+
+			clocks = <&xtcxo>,
+				 <&cmu_top DOUT_CLKCMU_DPUM_BUS>;
+			clock-names = "oscclk", "bus";
+		};
+
 		cmu_core: clock-controller@1b030000 {
 			compatible = "samsung,exynosautov9-cmu-core";
 			reg = <0x1b030000 0x8000>;

-- 
2.39.2

[PATCH v3 3/3] clk: samsung: exynosautov9: add dpum clock support

[Kwanghoon Son]

Add dpum clock for exynosautov9.

Signed-off-by: Kwanghoon Son <k.son@samsung.com>
---
 drivers/clk/samsung/clk-exynosautov9.c | 83 ++++++++++++++++++++++++++++++++++
 1 file changed, 83 insertions(+)

diff --git a/drivers/clk/samsung/clk-exynosautov9.c b/drivers/clk/samsung/clk-exynosautov9.c
index f04bacacab2c..5971e680e566 100644
--- a/drivers/clk/samsung/clk-exynosautov9.c
+++ b/drivers/clk/samsung/clk-exynosautov9.c
@@ -20,6 +20,7 @@
 #define CLKS_NR_TOP			(GOUT_CLKCMU_PERIS_BUS + 1)
 #define CLKS_NR_BUSMC			(CLK_GOUT_BUSMC_SPDMA_PCLK + 1)
 #define CLKS_NR_CORE			(CLK_GOUT_CORE_CMU_CORE_PCLK + 1)
+#define CLKS_NR_DPUM			(CLK_GOUT_DPUM_SYSMMU_D3_CLK + 1)
 #define CLKS_NR_FSYS0			(CLK_GOUT_FSYS0_PCIE_GEN3B_4L_CLK + 1)
 #define CLKS_NR_FSYS1			(CLK_GOUT_FSYS1_USB30_1_ACLK + 1)
 #define CLKS_NR_FSYS2			(CLK_GOUT_FSYS2_UFS_EMBD1_UNIPRO + 1)
@@ -1076,6 +1077,85 @@ static const struct samsung_cmu_info core_cmu_info __initconst = {
 	.clk_name		= "dout_clkcmu_core_bus",
 };
 
+/* ---- CMU_DPUM ---------------------------------------------------------- */
+
+/* Register Offset definitions for CMU_DPUM (0x18c00000) */
+#define PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER				0x0600
+#define CLK_CON_DIV_DIV_CLK_DPUM_BUSP					0x1800
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON		0x202c
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA		0x2030
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP		0x2034
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1	0x207c
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1	0x2084
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1	0x208c
+#define CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1	0x2094
+
+static const unsigned long dpum_clk_regs[] __initconst = {
+	PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER,
+	CLK_CON_DIV_DIV_CLK_DPUM_BUSP,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1,
+	CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1,
+};
+
+PNAME(mout_dpum_bus_user_p) = { "oscclk", "dout_clkcmu_dpum_bus" };
+
+static const struct samsung_mux_clock dpum_mux_clks[] __initconst = {
+	MUX(CLK_MOUT_DPUM_BUS_USER, "mout_dpum_bus_user",
+	    mout_dpum_bus_user_p, PLL_CON0_MUX_CLKCMU_DPUM_BUS_USER, 4, 1),
+};
+
+static const struct samsung_div_clock dpum_div_clks[] __initconst = {
+	DIV(CLK_DOUT_DPUM_BUSP, "dout_dpum_busp", "mout_dpum_bus_user",
+	    CLK_CON_DIV_DIV_CLK_DPUM_BUSP, 0, 3),
+};
+
+static const struct samsung_gate_clock dpum_gate_clks[] __initconst = {
+	GATE(CLK_GOUT_DPUM_ACLK_DECON, "gout_dpum_decon_aclk",
+	     "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DECON, 21,
+	     0, 0),
+	GATE(CLK_GOUT_DPUM_ACLK_DMA, "gout_dpum_dma_aclk", "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DMA, 21,
+	     0, 0),
+	GATE(CLK_GOUT_DPUM_ACLK_DPP, "gout_dpum_dpp_aclk", "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_DPUM_IPCLKPORT_ACLK_DPP, 21,
+	     0, 0),
+	GATE(CLK_GOUT_DPUM_SYSMMU_D0_CLK, "gout_dpum_sysmmu_d0_clk",
+	     "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D0_DPUM_IPCLKPORT_CLK_S1, 21,
+	     0, 0),
+	GATE(CLK_GOUT_DPUM_SYSMMU_D1_CLK, "gout_dpum_sysmmu_d1_clk",
+	     "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D1_DPUM_IPCLKPORT_CLK_S1, 21,
+	     0, 0),
+	GATE(CLK_GOUT_DPUM_SYSMMU_D2_CLK, "gout_dpum_sysmmu_d2_clk",
+	     "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D2_DPUM_IPCLKPORT_CLK_S1, 21,
+	     0, 0),
+	GATE(CLK_GOUT_DPUM_SYSMMU_D3_CLK, "gout_dpum_sysmmu_d3_clk",
+	     "mout_dpum_bus_user",
+	     CLK_CON_GAT_GOUT_BLK_DPUM_UID_SYSMMU_D3_DPUM_IPCLKPORT_CLK_S1, 21,
+	     0, 0),
+};
+
+static const struct samsung_cmu_info dpum_cmu_info __initconst = {
+	.mux_clks		= dpum_mux_clks,
+	.nr_mux_clks		= ARRAY_SIZE(dpum_mux_clks),
+	.div_clks		= dpum_div_clks,
+	.nr_div_clks		= ARRAY_SIZE(dpum_div_clks),
+	.gate_clks		= dpum_gate_clks,
+	.nr_gate_clks		= ARRAY_SIZE(dpum_gate_clks),
+	.nr_clk_ids		= CLKS_NR_DPUM,
+	.clk_regs		= dpum_clk_regs,
+	.nr_clk_regs		= ARRAY_SIZE(dpum_clk_regs),
+	.clk_name		= "bus",
+};
+
 /* ---- CMU_FSYS0 ---------------------------------------------------------- */
 
 /* Register Offset definitions for CMU_FSYS2 (0x17700000) */
@@ -2085,6 +2165,9 @@ static const struct of_device_id exynosautov9_cmu_of_match[] = {
 	}, {
 		.compatible = "samsung,exynosautov9-cmu-core",
 		.data = &core_cmu_info,
+	}, {
+		.compatible = "samsung,exynosautov9-cmu-dpum",
+		.data = &dpum_cmu_info,
 	}, {
 		.compatible = "samsung,exynosautov9-cmu-fsys0",
 		.data = &fsys0_cmu_info,

-- 
2.39.2

Re: (subset) [PATCH v3 1/3] dt-bindings: clock: exynosautov9: add dpum clock

[Krzysztof Kozlowski]

On Fri, 09 Aug 2024 20:54:12 +0900, Kwanghoon Son wrote:
> Add dpum clock definitions and compatibles.
> 
> Also used clock name 'bus' instead of full clock name
> dout_clkcmu_dpum_bus like other board cmu schema (GS101).
> 
> 

Applied, thanks!

[1/3] dt-bindings: clock: exynosautov9: add dpum clock
      https://git.kernel.org/krzk/linux/c/ccb41c445a3e9506ef43fe33867a356048e41477

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Re: (subset) [PATCH v3 3/3] clk: samsung: exynosautov9: add dpum clock support

[Krzysztof Kozlowski]

On Fri, 09 Aug 2024 20:54:14 +0900, Kwanghoon Son wrote:
> Add dpum clock for exynosautov9.
> 
> 

Applied, thanks!

[3/3] clk: samsung: exynosautov9: add dpum clock support
      https://git.kernel.org/krzk/linux/c/ae07389413d41995a027aa5fb99938cd9201fb40

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Re: (subset) [PATCH v3 2/3] arm64: dts: exynosautov9: add dpum clock DT nodes

[Krzysztof Kozlowski]

On Fri, 09 Aug 2024 20:54:13 +0900, Kwanghoon Son wrote:
> Add dpum clock for sysmmu, dpu.
> 
> 

Applied, thanks!

[2/3] arm64: dts: exynosautov9: add dpum clock DT nodes
      https://git.kernel.org/krzk/linux/c/2cc6b908f800bd6440cc57c1c692449fab49168b

Best regards,
-- 
Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>

Re: [PATCH v3 0/3] dpum clock support for Exynos Auto v9 SoC

[David Virag]

Hi Kwanghoon,

On Fri, 2024-08-09 at 20:54 +0900, Kwanghoon Son wrote:
> DPUM (Display Processing Unit Main) is main dpu for Exynosautov9.
>     
> This patches enable clock for dpum, sysmmu(iommu).
> 
> I tested using sysmmu, DPP, DECON, DP on sdk board (modetest works).

Does this mean you are working on mainline drivers for these?

If you don't mind me asking, what state are these in?
Is DSIM being worked on?

I am asking these, because I am also working on some drivers for DPP,
DECON, and DSIM on the Exynos7885.

Now, my DPP and DECON drivers are not even close to complete, they just
have the bare minimum for output and vsync, using them as initialized
by the bootloader, but I do have a semi-functional DSIM driver (well,
existing mainline DSIM driver patched up to work on 7885) that is
enough for controlling the DSI panel attached to my phone.

If you are working on DPP and DECON drivers, I won't spend much time
with those for now, as your driver for ExynosAutoV9 may help a lot with
7885 as well.

If you are not working on a DSIM driver, I'll keep working on it for
7885. If you are, I'll have to think about how to move forward.

Best regards,
David

Re: [PATCH v3 0/3] dpum clock support for Exynos Auto v9 SoC

[Kwanghoon Son]

On Thu, 2024-08-22 at 20:59 +0200, David Virag wrote:
> Hi Kwanghoon,
> 
> On Fri, 2024-08-09 at 20:54 +0900, Kwanghoon Son wrote:
> > DPUM (Display Processing Unit Main) is main dpu for Exynosautov9.
> >     
> > This patches enable clock for dpum, sysmmu(iommu).
> > 
> > I tested using sysmmu, DPP, DECON, DP on sdk board (modetest works).
> 
> Does this mean you are working on mainline drivers for these?

Yes. I working on decon exynosautov9 now. (maybe exynosautov920 in
future..)

> If you don't mind me asking, what state are these in?

I'm glad to.
I shift vendor code to mainline. vendor code had split directory, now I
merged to proper mainline drm directory. And it work with modetest. But
a lot of todo.. It's 'somehow' works level.

> Is DSIM being worked on?

For now No. Exynosauto series support DP, MIPI both, but SDK board is
shape of easy to test with DP. For now only modetest works through DP
port interface.

> I am asking these, because I am also working on some drivers for DPP,
> DECON, and DSIM on the Exynos7885.

Ah, that's nice. But actually I'm not involved with exynosauto or the
hardware team. (But I get board and information from them to upstream.)
So I have no idea what the Exynos7885 drm hardware has.

> Now, my DPP and DECON drivers are not even close to complete, they just
> have the bare minimum for output and vsync, using them as initialized
> by the bootloader, but I do have a semi-functional DSIM driver (well,
> existing mainline DSIM driver patched up to work on 7885) that is
> enough for controlling the DSI panel attached to my phone.

For now, I don't understands how your display works because I really
don't know about 7885. But my DPP and decon also far to complete.
(really ugly code.)

> If you are working on DPP and DECON drivers, I won't spend much time
> with those for now, as your driver for ExynosAutoV9 may help a lot with
> 7885 as well.

Here is my suggestion. I will share my code after clean up with NO-
MERGE or WIP tag ASAP. But mind that I only code kernel when have spare
time..

Could you share your code also? even It's not ready.

> If you are not working on a DSIM driver, I'll keep working on it for
> 7885. If you are, I'll have to think about how to move forward.
> 
> Best regards,
> David

+ I added Sam Protsenko <semen.protsenko@linaro.org>
Because I also want to know maybe he has some process for drm, since he
worked on exynos850 sysmmu.

+ Alim Akhtar, Do you know some information around theses?
Especially between 7885, exynosauto?

Re: [PATCH v3 0/3] dpum clock support for Exynos Auto v9 SoC

[Sam Protsenko]

On Fri, Aug 23, 2024 at 9:56 AM Kwanghoon Son <kwangson@yahoo.com> wrote:

[snip]

>
> > If you are not working on a DSIM driver, I'll keep working on it for
> > 7885. If you are, I'll have to think about how to move forward.
> >
> > Best regards,
> > David
>
> + I added Sam Protsenko <semen.protsenko@linaro.org>
> Because I also want to know maybe he has some process for drm, since he
> worked on exynos850 sysmmu.
>

I'm not working on DRM at the moment. After enabling SysMMU I've
switched to other Exynos tasks, not related to graphics. FWIW, I've
implemented the test driver for SysMMU, which you can use to verify
your SysMMU driver is functional. It's able to perform address
translations initiated from the test driver (using regular CPU). That
way you can test your SysMMU without DPU or other IP blocks initiating
the translation. You can find SysMMU test driver in GitHub repo [1],
and the commit adding the driver is [2].

All that said, I'd be excited to see DRM working on Exynos850 some
day! So please keep me in the loop, and let me know if I can help
somehow (by testing the code, etc).

Thanks!

[1] https://github.com/joe-skb7/linux/tree/e850-96-mainline-iommu
[2] https://github.com/joe-skb7/linux/commit/d712fb52a12ac0958118f9c23a4f1f0d7b9276a7

[snip]