From: James Morse <james.morse@arm.com>
To: Borislav Petkov <bp@alien8.de>
Cc: Tyler Baicar <baicar.tyler@gmail.com>,
Tyler Baicar <tbaicar@codeaurora.org>,
wufan@codeaurora.org,
Linux Kernel Mailing List <linux-kernel@vger.kernel.org>,
harba@qti.qualcomm.com, mchehab@kernel.org,
arm-mail-list <linux-arm-kernel@lists.infradead.org>,
linux-edac@vger.kernel.org
Subject: Re: [RFC PATCH] EDAC, ghes: Enable per-layer error reporting for ARM
Date: Wed, 29 Aug 2018 11:20:48 +0100 [thread overview]
Message-ID: <2e7b984a-8f8f-dad7-4ee5-043dd236a9b1@arm.com> (raw)
In-Reply-To: <20180829073804.GA6843@nazgul.tnic>
Hi Boris,
On 29/08/18 08:38, Borislav Petkov wrote:
> On Tue, Aug 28, 2018 at 06:09:24PM +0100, James Morse wrote:
>> Does x86 have another source of memory-topology information it needs to
>> correlate smbios with?
>
> Bah, pinpointing the DIMM on x86 is a mess. There's no reliable way to
> say which DIMM it is in certain cases (interleaving, mirrorring, ...)
> and it is all platform-dependent. So we do the layers to dump a memory
> location (node, memory controller, ....) so that we can at least limit
> the number of DIMMs the user needs to replace/try.
Right. I'd like ghes-edac to work in the same way for both architectures.
I think this is best done by stuffing the dmi-handle in struct dimm_info during
ghes_edac_dmidecode(), then populating the struct edac_raw_error_desc layers
from the matching mci->dimms 'location'.
For EDAC_MC_LAYER_ALL_MEM this boils down to a flat index, so pointer arithmetic
on mci->dimms is an appropriate short cut.
(We should probably 'FIXME: It shouldn't be hard to also fill the DIMM labels'
at the same time so that no-one is tempted to interpret the edac:dimm-idx)
> In an ideal world, I'd like to be able to query the SPD chips on the
(oh, that can be done?)
> DIMMs and build the topology and then when an error happens to say,
> "error in DIMM <silkscreen>" where silkscreen is what is written on the
> motherboard under the DIMM socket.
>
> But I don't see that happening any time soon...
>> For arm there is nothing else describing the memory-topology, so as long as we
>> can correlate the smbios table and ghes:cper records through the handles, we can
>> get this working for all systems.
>
> And then make sure vendors fill in the proper info in smbios. Because that's
> also a mess on x86.
I got educated by the people who look after specifications last time I touched
this [0]. SMBIOS tables are required by Arm's 'Server Base Boot Requirements',
It lists the memory-device and physical-memory-array as required.
I will drop them a note that we will be depending on the handle, and it should
go on the list too... if its not populated on today's systems we can fall back
to !e->enable_per_layer_report as we do today.
Thanks,
James
[0] https://www.spinics.net/lists/arm-kernel/msg653133.html
next prev parent reply other threads:[~2018-08-29 10:20 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2018-07-16 17:26 Tyler Baicar
2018-07-19 14:01 ` Borislav Petkov
2018-07-19 14:46 ` James Morse
2018-07-19 18:36 ` Tyler Baicar
2018-07-20 4:10 ` Borislav Petkov
2018-08-23 9:28 ` James Morse
2018-08-23 15:46 ` Tyler Baicar
2018-08-24 9:48 ` James Morse
2018-08-24 12:01 ` Borislav Petkov
2018-08-28 17:09 ` James Morse
2018-08-29 7:38 ` Borislav Petkov
2018-08-29 10:20 ` James Morse [this message]
2018-08-30 10:28 ` Borislav Petkov
2018-08-24 14:30 ` wufan
2018-08-28 17:09 ` James Morse
2018-08-24 15:14 ` Tyler Baicar
2018-08-28 17:11 ` James Morse
2018-08-28 20:04 ` Tyler Baicar
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