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From: Jie Gan <quic_jiegan@quicinc.com>
To: Krzysztof Kozlowski <krzk@kernel.org>,
	Jie Gan <jie.gan@oss.qualcomm.com>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	Mike Leach <mike.leach@linaro.org>,
	James Clark <james.clark@linaro.org>,
	Rob Herring <robh@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Conor Dooley <conor+dt@kernel.org>,
	Bjorn Andersson <andersson@kernel.org>,
	Konrad Dybcio <konradybcio@kernel.org>
Cc: <coresight@lists.linaro.org>,
	<linux-arm-kernel@lists.infradead.org>,
	<linux-arm-msm@vger.kernel.org>, <devicetree@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>
Subject: Re: [PATCH v2 0/2] Enable CTCU device for QCS8300
Date: Fri, 4 Jul 2025 16:07:41 +0800	[thread overview]
Message-ID: <2e8366b3-c060-4bb8-9704-0a8f41901706@quicinc.com> (raw)
In-Reply-To: <3551dba1-0c5f-4000-8b95-6a04cd81a027@kernel.org>



On 7/4/2025 3:54 PM, Krzysztof Kozlowski wrote:
> On 25/06/2025 02:59, Jie Gan wrote:
>>
>>
>> On 6/24/2025 5:59 PM, Jie Gan wrote:
>>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in binding to utilize
>>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 shares same
>>> configurations as SA8775p platform.
>>
>> Hi dear maintainers,
>>
>> I just realized it would be more efficient to introduce a common
>> compatible string for SoCs that include two TMC ETR devices.
>>
>> Most of these SoCs share the same CTCU data configuration, such as the
> 
> "Most" basically disqualifies your idea.

Okay, it's not a proper expression.
SoCs included two ETR devices shared same configuration. So I think use 
a common compatible for these SoCs is make sense for me and dont need to 
update the dt-binding again and again...

I will send a new patch to address this idea if it's acceptable.

> 
>> offsets for the ATID and IRQ registers, because they integrate the same
>> version of the CTCU hardware.
>>
>> So I propose introducing a common compatible string,
>> "coresight-ctcu-v2", to simplify the device tree configuration for these
>> platforms.
> 
> This is explained in writing bindings.

Yeah, explained in the code lines..

Thanks,
Jie

> 
> Best regards,
> Krzysztof


  reply	other threads:[~2025-07-04  8:07 UTC|newest]

Thread overview: 16+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-24  9:59 Jie Gan
2025-06-24  9:59 ` [PATCH v2 1/2] dt-bindings: arm: add " Jie Gan
2025-06-24  9:59 ` [PATCH v2 2/2] arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes Jie Gan
2025-06-25  0:59 ` [PATCH v2 0/2] Enable CTCU device for QCS8300 Jie Gan
2025-07-04  2:41   ` Jie Gan
2025-07-04  7:54   ` Krzysztof Kozlowski
2025-07-04  8:07     ` Jie Gan [this message]
2025-07-04  8:10       ` Krzysztof Kozlowski
2025-07-04  8:14         ` Jie Gan
2025-07-15  0:38           ` Jie Gan
2025-07-15  0:41 ` Jie Gan
2025-07-28  1:08   ` Jie Gan
2025-08-05  4:11     ` Jie Gan
2025-08-05  9:53       ` Mike Leach
2025-08-05 10:25         ` Jie Gan
2025-08-25  1:32           ` Jie Gan

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