Re: [PATCH v2 0/2] Enable CTCU device for QCS8300

[Jie Gan <quic_jiegan@quicinc.com>]

On 6/25/2025 8:59 AM, Jie Gan wrote:
> 
> 
> On 6/24/2025 5:59 PM, Jie Gan wrote:
>> Enable CTCU device for QCS8300 platform. Add a fallback mechnasim in 
>> binding to utilize
>> the compitable of the SA8775p platform becuase the CTCU for QCS8300 
>> shares same
>> configurations as SA8775p platform.
> 
> Hi dear maintainers,
> 
> I just realized it would be more efficient to introduce a common 
> compatible string for SoCs that include two TMC ETR devices.
> 
> Most of these SoCs share the same CTCU data configuration, such as the 
> offsets for the ATID and IRQ registers, because they integrate the same 
> version of the CTCU hardware.
> 
> So I propose introducing a common compatible string, "coresight-ctcu- 
> v2", to simplify the device tree configuration for these platforms.
> 
> Here is the new dt-binding format:
> 
> properties:
>    compatible:
>      oneOf:
>        - items:
>            - enum:
>                - qcom,sa8775p-ctcu
>                - qcom,qcs8300-ctcu
>            - const: qcom,coresight-ctcu-v2
>        - enum:
>            - qcom,coresight-ctcu-v2
> 
> Thanks,
> Jie

Gentle ping.

Thanks,
Jie

> 
>>
>> Changes in V2:
>> 1. Add Krzysztof's R-B tag for dt-binding patch.
>> 2. Add Konrad's Acked-by tag for dt patch.
>> 3. Rebased on tag next-20250623.
>> 4. Missed email addresses for coresight's maintainers in V1, loop them.
>> Link to V1 - https://lore.kernel.org/all/20250327024943.3502313-1- 
>> jie.gan@oss.qualcomm.com/
>>
>> Jie Gan (2):
>>    dt-bindings: arm: add CTCU device for QCS8300
>>    arm64: dts: qcom: qcs8300: Add CTCU and ETR nodes
>>
>>   .../bindings/arm/qcom,coresight-ctcu.yaml     |   9 +-
>>   arch/arm64/boot/dts/qcom/qcs8300.dtsi         | 153 ++++++++++++++++++
>>   2 files changed, 160 insertions(+), 2 deletions(-)
>>
> 
>