* [PATCH] clk: qcom: gcc-x1e80100: Use BRANCH_HALT_DELAY for UFS PHY symbol
@ 2025-11-19 17:53 Taniya Das
2025-11-20 9:19 ` Konrad Dybcio
2025-11-20 11:52 ` Abel Vesa
0 siblings, 2 replies; 3+ messages in thread
From: Taniya Das @ 2025-11-19 17:53 UTC (permalink / raw)
To: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rajendra Nayak,
Abel Vesa, Konrad Dybcio, Sibi Sankar
Cc: Ajit Pandey, Imran Shaik, Jagadeesh Kona, Bryan O'Donoghue,
linux-arm-msm, linux-clk, linux-kernel, Taniya Das
Switch the halt_check method from BRANCH_HALT to BRANCH_HALT_DELAY for
gcc_ufs_phy_rx_symbol_0_clk, gcc_ufs_phy_rx_symbol_1_clk, and
gcc_ufs_phy_tx_symbol_0_clk. These clocks are externally sourced and do
not require polling for halt status.
Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
---
drivers/clk/qcom/gcc-x1e80100.c | 6 +++---
1 file changed, 3 insertions(+), 3 deletions(-)
diff --git a/drivers/clk/qcom/gcc-x1e80100.c b/drivers/clk/qcom/gcc-x1e80100.c
index b63c8abdd2fc24fc963f038f8cdcafd7598ba989..0ebcecd2b7e0898cd8803676cdd1d7d640f770a3 100644
--- a/drivers/clk/qcom/gcc-x1e80100.c
+++ b/drivers/clk/qcom/gcc-x1e80100.c
@@ -5148,7 +5148,7 @@ static struct clk_branch gcc_ufs_phy_phy_aux_clk = {
static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
.halt_reg = 0x7702c,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x7702c,
.enable_mask = BIT(0),
@@ -5161,7 +5161,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = {
static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
.halt_reg = 0x770cc,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x770cc,
.enable_mask = BIT(0),
@@ -5174,7 +5174,7 @@ static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = {
static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = {
.halt_reg = 0x77028,
- .halt_check = BRANCH_HALT,
+ .halt_check = BRANCH_HALT_DELAY,
.clkr = {
.enable_reg = 0x77028,
.enable_mask = BIT(0),
---
base-commit: 187dac290bfd0741b9d7d5490af825c33fd9baa4
change-id: 20251119-gcc_ufs_phy_clk_branch_delay-26688f483309
Best regards,
--
Taniya Das <taniya.das@oss.qualcomm.com>
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: qcom: gcc-x1e80100: Use BRANCH_HALT_DELAY for UFS PHY symbol
2025-11-19 17:53 [PATCH] clk: qcom: gcc-x1e80100: Use BRANCH_HALT_DELAY for UFS PHY symbol Taniya Das
@ 2025-11-20 9:19 ` Konrad Dybcio
2025-11-20 11:52 ` Abel Vesa
1 sibling, 0 replies; 3+ messages in thread
From: Konrad Dybcio @ 2025-11-20 9:19 UTC (permalink / raw)
To: Taniya Das, Bjorn Andersson, Michael Turquette, Stephen Boyd,
Rajendra Nayak, Abel Vesa, Konrad Dybcio, Sibi Sankar
Cc: Ajit Pandey, Imran Shaik, Jagadeesh Kona, Bryan O'Donoghue,
linux-arm-msm, linux-clk, linux-kernel
On 11/19/25 6:53 PM, Taniya Das wrote:
> Switch the halt_check method from BRANCH_HALT to BRANCH_HALT_DELAY for
> gcc_ufs_phy_rx_symbol_0_clk, gcc_ufs_phy_rx_symbol_1_clk, and
> gcc_ufs_phy_tx_symbol_0_clk. These clocks are externally sourced and do
> not require polling for halt status.
>
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
> ---
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Konrad
^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] clk: qcom: gcc-x1e80100: Use BRANCH_HALT_DELAY for UFS PHY symbol
2025-11-19 17:53 [PATCH] clk: qcom: gcc-x1e80100: Use BRANCH_HALT_DELAY for UFS PHY symbol Taniya Das
2025-11-20 9:19 ` Konrad Dybcio
@ 2025-11-20 11:52 ` Abel Vesa
1 sibling, 0 replies; 3+ messages in thread
From: Abel Vesa @ 2025-11-20 11:52 UTC (permalink / raw)
To: Taniya Das
Cc: Bjorn Andersson, Michael Turquette, Stephen Boyd, Rajendra Nayak,
Konrad Dybcio, Sibi Sankar, Ajit Pandey, Imran Shaik,
Jagadeesh Kona, Bryan O'Donoghue, linux-arm-msm, linux-clk,
linux-kernel
On 25-11-19 23:23:03, Taniya Das wrote:
> Switch the halt_check method from BRANCH_HALT to BRANCH_HALT_DELAY for
> gcc_ufs_phy_rx_symbol_0_clk, gcc_ufs_phy_rx_symbol_1_clk, and
> gcc_ufs_phy_tx_symbol_0_clk. These clocks are externally sourced and do
> not require polling for halt status.
>
> Fixes: 161b7c401f4b ("clk: qcom: Add Global Clock controller (GCC) driver for X1E80100")
> Signed-off-by: Taniya Das <taniya.das@oss.qualcomm.com>
Reviewed-by: Abel Vesa <abel.vesa@linaro.org>
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2025-11-20 11:52 UTC | newest]
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2025-11-19 17:53 [PATCH] clk: qcom: gcc-x1e80100: Use BRANCH_HALT_DELAY for UFS PHY symbol Taniya Das
2025-11-20 9:19 ` Konrad Dybcio
2025-11-20 11:52 ` Abel Vesa
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