* [PATCH v3 01/10] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-05 12:11 ` Krzysztof Kozlowski
2026-06-01 12:55 ` [PATCH v3 02/10] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible Komal Bajaj
` (8 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Document the GPI DMA engine on Shikra platform.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
index 8f9a552fe30e..54dca623223d 100644
--- a/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
+++ b/Documentation/devicetree/bindings/dma/qcom,gpi.yaml
@@ -37,6 +37,7 @@ properties:
- qcom,sc7280-gpi-dma
- qcom,sc8280xp-gpi-dma
- qcom,sdx75-gpi-dma
+ - qcom,shikra-gpi-dma
- qcom,sm6115-gpi-dma
- qcom,sm6375-gpi-dma
- qcom,sm8350-gpi-dma
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 01/10] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC
2026-06-01 12:55 ` [PATCH v3 01/10] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC Komal Bajaj
@ 2026-06-05 12:11 ` Krzysztof Kozlowski
0 siblings, 0 replies; 23+ messages in thread
From: Krzysztof Kozlowski @ 2026-06-05 12:11 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Xueyao An
On Mon, Jun 01, 2026 at 06:25:03PM +0530, Komal Bajaj wrote:
> From: Xueyao An <xueyao.an@oss.qualcomm.com>
>
> Document the GPI DMA engine on Shikra platform.
Compatible with?
>
> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/dma/qcom,gpi.yaml | 1 +
> 1 file changed, 1 insertion(+)
With extended commit msg:
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 02/10] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 01/10] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-05 12:12 ` Krzysztof Kozlowski
2026-06-01 12:55 ` [PATCH v3 03/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra Komal Bajaj
` (7 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR
bandwidth monitor. Shikra has a BWMONv5 for CPU.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 +
1 file changed, 1 insertion(+)
diff --git a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
index ff64225e8281..8f6c937e44ce 100644
--- a/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
+++ b/Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml
@@ -52,6 +52,7 @@ properties:
- qcom,sa8775p-llcc-bwmon
- qcom,sc7180-llcc-bwmon
- qcom,sc8280xp-llcc-bwmon
+ - qcom,shikra-cpu-bwmon
- qcom,sm6350-cpu-bwmon
- qcom,sm8250-llcc-bwmon
- qcom,sm8550-llcc-bwmon
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 02/10] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible
2026-06-01 12:55 ` [PATCH v3 02/10] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible Komal Bajaj
@ 2026-06-05 12:12 ` Krzysztof Kozlowski
0 siblings, 0 replies; 23+ messages in thread
From: Krzysztof Kozlowski @ 2026-06-05 12:12 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Georgi Djakov, Bjorn Andersson, Konrad Dybcio,
linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Sayantan Chakraborty
On Mon, Jun 01, 2026 at 06:25:04PM +0530, Komal Bajaj wrote:
> From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
>
> Add the Qualcomm Shikra SoC compatible string for the CPU-to-DDR
> bandwidth monitor. Shikra has a BWMONv5 for CPU.
>
> Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> Documentation/devicetree/bindings/interconnect/qcom,msm8998-bwmon.yaml | 1 +
> 1 file changed, 1 insertion(+)
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 03/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 01/10] dt-bindings: dma: qcom,gpi: Document GPI DMA engine for Shikra SoC Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 02/10] dt-bindings: interconnect: qcom-bwmon: Add Shikra cpu-bwmon compatible Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-06 12:46 ` Dmitry Baryshkov
2026-06-01 12:55 ` [PATCH v3 04/10] arm64: dts: qcom: shikra: Add DDR BWMON support Komal Bajaj
` (6 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Xueyao An
From: Xueyao An <xueyao.an@oss.qualcomm.com>
Add device tree support for QUPv3 serial engine protocols on Shikra.
Shikra has 10 QUP serial engines under a single QUP wrapper, all with
support of GPI DMA engines.
Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++++++++++
1 file changed, 951 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index a4334d99c1f3..e6ec07a865f0 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
@@ -348,6 +349,161 @@ tlmm: pinctrl@500000 {
gpio-ranges = <&tlmm 0 0 165>;
wakeup-parent = <&mpm>;
+ qup_i2c0_data_clk: qup-i2c0-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio2", "gpio3";
+ function = "qup0_se0";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c1_data_clk: qup-i2c1-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c2_data_clk: qup-i2c2-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c3_data_clk: qup-i2c3-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c4_data_clk: qup-i2c4-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c5_data_clk: qup-i2c5-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c6_data_clk: qup-i2c6-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c7_data_clk: qup-i2c7-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c8_data_clk: qup-i2c8-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_i2c9_data_clk: qup-i2c9-data-clk-state {
+ /* SDA, SCL */
+ pins = "gpio27", "gpio26";
+ function = "qup0_se9_01";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_spi0_cs: qup-spi0-cs-state {
+ pins = "gpio1";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi0_data_clk: qup-spi0-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio2", "gpio3", "gpio0";
+ function = "qup0_se0";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_cs: qup-spi2-cs-state {
+ pins = "gpio9";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi2_data_clk: qup-spi2-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio6", "gpio7", "gpio8";
+ function = "qup0_se2";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_cs: qup-spi5-cs-state {
+ pins = "gpio17";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi5_data_clk: qup-spi5-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio14", "gpio15", "gpio16";
+ function = "qup0_se5";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_cs: qup-spi6-cs-state {
+ pins = "gpio29";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi6_data_clk: qup-spi6-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio18", "gpio19", "gpio28";
+ function = "qup0_se6";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_cs: qup-spi8-cs-state {
+ pins = "gpio25";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
+ qup_spi8_data_clk: qup-spi8-data-clk-state {
+ /* MISO, MOSI, CLK */
+ pins = "gpio22", "gpio23", "gpio24";
+ function = "qup0_se8";
+ drive-strength = <6>;
+ bias-disable;
+ };
+
qup_uart0_default: qup-uart0-default-state {
pins = "gpio0", "gpio1";
function = "qup0_se0";
@@ -355,6 +511,105 @@ qup_uart0_default: qup-uart0-default-state {
bias-disable;
};
+ qup_uart1_default: qup-uart1-default-state {
+ pins = "gpio4", "gpio5";
+ function = "qup0_se1_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart2_default: qup-uart2-default-state {
+ /* TX, RX */
+ pins = "gpio8", "gpio9";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart2_cts_rts: qup-uart2-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio6", "gpio7";
+ function = "qup0_se2";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart3_default: qup-uart3-default-state {
+ pins = "gpio10", "gpio11";
+ function = "qup0_se3_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart4_default: qup-uart4-default-state {
+ pins = "gpio12", "gpio13";
+ function = "qup0_se4_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart5_default: qup-uart5-default-state {
+ /* TX, RX */
+ pins = "gpio16", "gpio17";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart5_cts_rts: qup-uart5-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio14", "gpio15";
+ function = "qup0_se5";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart6_default: qup-uart6-default-state {
+ /* TX, RX */
+ pins = "gpio28", "gpio29";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart6_cts_rts: qup-uart6-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio18", "gpio19";
+ function = "qup0_se6";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart7_default: qup-uart7-default-state {
+ pins = "gpio20", "gpio21";
+ function = "qup0_se7_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
+ qup_uart8_default: qup-uart8-default-state {
+ /* TX, RX */
+ pins = "gpio24", "gpio25";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-up;
+ };
+
+ qup_uart8_cts_rts: qup-uart8-cts-rts-state {
+ /* CTS, RTS */
+ pins = "gpio22", "gpio23";
+ function = "qup0_se8";
+ drive-strength = <2>;
+ bias-pull-down;
+ };
+
+ qup_uart9_default: qup-uart9-default-state {
+ pins = "gpio26", "gpio27";
+ function = "qup0_se9_23";
+ drive-strength = <2>;
+ bias-disable;
+ };
+
sdc1_state_on: sdc1-on-state {
clk-pins {
pins = "sdc1_clk";
@@ -604,6 +859,34 @@ opp-384000000 {
};
};
+ gpi_dma0: dma-controller@4a00000 {
+ compatible = "qcom,shikra-gpi-dma", "qcom,sm6350-gpi-dma";
+ reg = <0x0 0x04a00000 0x0 0x60000>;
+
+ interrupts = <GIC_SPI 511 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 512 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 513 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 514 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 515 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 516 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 517 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 518 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 519 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 520 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 521 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 522 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 523 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 524 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 525 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 526 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ dma-channels = <16>;
+ dma-channel-mask = <0xff>;
+ #dma-cells = <3>;
+
+ iommus = <&apps_smmu 0xf6 0x0>;
+ };
+
qupv3_0: geniqup@4ac0000 {
compatible = "qcom,geni-se-qup";
reg = <0x0 0x04ac0000 0x0 0x2000>;
@@ -613,10 +896,75 @@ qupv3_0: geniqup@4ac0000 {
clock-names = "m-ahb",
"s-ahb";
+ iommus = <&apps_smmu 0xe3 0x0>;
+
#address-cells = <2>;
#size-cells = <2>;
ranges;
+ status = "disabled";
+
+ i2c0: i2c@4a80000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 0 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c0_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi0: spi@4a80000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a80000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 527 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S0_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 0 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 0 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi0_data_clk>, <&qup_spi0_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
uart0: serial@4a80000 {
compatible = "qcom,geni-debug-uart";
reg = <0x0 0x04a80000 0x0 0x4000>;
@@ -638,6 +986,609 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
status = "disabled";
};
+
+ i2c1: i2c@4a84000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 1 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 1 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c1_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart1: serial@4a84000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a84000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 528 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S1_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart1_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c2: i2c@4a88000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ pinctrl-0 = <&qup_i2c2_data_clk>;
+ pinctrl-names = "default";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 2 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi2: spi@4a88000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a88000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 2 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 2 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi2_data_clk>, <&qup_spi2_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart2: serial@4a88000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a88000 0x0 0x4000>;
+
+ interrupts-extended = <&intc GIC_SPI 529 IRQ_TYPE_LEVEL_HIGH 0>,
+ <&tlmm 9 IRQ_TYPE_LEVEL_HIGH>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S2_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart2_default>, <&qup_uart2_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c3: i2c@4a8c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 3 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 3 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c3_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart3: serial@4a8c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a8c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S3_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart3_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c4: i2c@4a90000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 4 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 4 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c4_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart4: serial@4a90000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a90000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 531 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S4_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart4_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c5: i2c@4a94000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 5 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c5_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi5: spi@4a94000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 5 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 5 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi5_data_clk>, <&qup_spi5_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart5: serial@4a94000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a94000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S5_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart5_default>, <&qup_uart5_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c6: i2c@4a98000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 6 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c6_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi6: spi@4a98000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 6 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 6 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi6_data_clk>, <&qup_spi6_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart6: serial@4a98000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a98000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S6_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart6_default>, <&qup_uart6_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c7: i2c@4a9c000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 7 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 7 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c7_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart7: serial@4a9c000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04a9c000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 534 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S7_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart7_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c8: i2c@4aa0000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 8 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c8_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ spi8: spi@4aa0000 {
+ compatible = "qcom,geni-spi";
+ reg = <0x0 0x4aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ dmas = <&gpi_dma0 0 8 QCOM_GPI_SPI>,
+ <&gpi_dma0 1 8 QCOM_GPI_SPI>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_spi8_data_clk>, <&qup_spi8_cs>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart8: serial@4aa0000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa0000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 535 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S8_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart8_default>, <&qup_uart8_cts_rts>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
+
+ i2c9: i2c@4aa4000 {
+ compatible = "qcom,geni-i2c";
+ reg = <0x0 0x4aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>,
+ <&system_noc MASTER_QUP_0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config",
+ "qup-memory";
+
+ dmas = <&gpi_dma0 0 9 QCOM_GPI_I2C>,
+ <&gpi_dma0 1 9 QCOM_GPI_I2C>;
+ dma-names = "tx", "rx";
+
+ pinctrl-0 = <&qup_i2c9_data_clk>;
+ pinctrl-names = "default";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ status = "disabled";
+ };
+
+ uart9: serial@4aa4000 {
+ compatible = "qcom,geni-uart";
+ reg = <0x0 0x04aa4000 0x0 0x4000>;
+
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ clocks = <&gcc GCC_QUPV3_WRAP0_S9_CLK>;
+ clock-names = "se";
+
+ interconnects = <&clk_virt MASTER_QUP_CORE_0 RPM_ALWAYS_TAG
+ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
+ <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &config_noc SLAVE_QUP_0 RPM_ALWAYS_TAG>;
+ interconnect-names = "qup-core",
+ "qup-config";
+
+ pinctrl-0 = <&qup_uart9_default>;
+ pinctrl-names = "default";
+
+ status = "disabled";
+ };
};
sram@c11e000 {
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 03/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra
2026-06-01 12:55 ` [PATCH v3 03/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra Komal Bajaj
@ 2026-06-06 12:46 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2026-06-06 12:46 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Xueyao An
On Mon, Jun 01, 2026 at 06:25:05PM +0530, Komal Bajaj wrote:
> From: Xueyao An <xueyao.an@oss.qualcomm.com>
>
> Add device tree support for QUPv3 serial engine protocols on Shikra.
> Shikra has 10 QUP serial engines under a single QUP wrapper, all with
> support of GPI DMA engines.
>
> Signed-off-by: Xueyao An <xueyao.an@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra.dtsi | 951 +++++++++++++++++++++++++++++++++++
> 1 file changed, 951 insertions(+)
>
I didn't completely cross-check, but it looks good otherwise.
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 04/10] arm64: dts: qcom: shikra: Add DDR BWMON support
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (2 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 03/10] arm64: dts: qcom: Add QUPv3 configuration for Shikra Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 05/10] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables Komal Bajaj
` (5 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Sayantan Chakraborty, Konrad Dybcio,
Dmitry Baryshkov
From: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Add CPU-to-DDR BWMON nodes and their corresponding opp tables for
Shikra SoC. This is necessary to enable power management and optimize
system performance from the perspective of dynamically changing DDR
frequencies.
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 40 ++++++++++++++++++++++++++++++++++++
1 file changed, 40 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index e6ec07a865f0..ec1bfebed226 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -661,6 +661,46 @@ rclk-pins {
};
};
+ pmu@c91000 {
+ compatible = "qcom,shikra-cpu-bwmon", "qcom,sc7280-llcc-bwmon";
+ reg = <0x0 0x00c91000 0x0 0x1000>;
+
+ interrupts = <GIC_SPI 468 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>;
+
+ operating-points-v2 = <&cpu_bwmon_opp_table>;
+
+ cpu_bwmon_opp_table: opp-table {
+ compatible = "operating-points-v2";
+
+ opp-0 {
+ opp-peak-kBps = <1200000>;
+ };
+
+ opp-1 {
+ opp-peak-kBps = <2188000>;
+ };
+
+ opp-2 {
+ opp-peak-kBps = <3072000>;
+ };
+
+ opp-3 {
+ opp-peak-kBps = <4068000>;
+ };
+
+ opp-4 {
+ opp-peak-kBps = <6220000>;
+ };
+
+ opp-5 {
+ opp-peak-kBps = <7216000>;
+ };
+ };
+ };
+
mem_noc: interconnect@d00000 {
compatible = "qcom,shikra-mem-noc-core";
reg = <0x0 0x00d00000 0x0 0x43080>;
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v3 05/10] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (3 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 04/10] arm64: dts: qcom: shikra: Add DDR BWMON support Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 06/10] arm64: dts: qcom: shikra: Add SMP2P nodes Komal Bajaj
` (4 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Aastha Pandey, Imran Shaik, Raviteja Laggyshetty,
Sayantan Chakraborty, Konrad Dybcio, Dmitry Baryshkov
Add cpufreq-hw node to support cpufreq scaling on Qualcomm Shikra SoCs.
Also, add Epoch Subsystem (EPSS) L3 interconnect provider node and OPP
tables required to scale DDR and L3 per freq-domain on Shikra SoC.
Co-developed-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Signed-off-by: Aastha Pandey <aastha.pandey@oss.qualcomm.com>
Co-developed-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
Co-developed-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Signed-off-by: Raviteja Laggyshetty <raviteja.laggyshetty@oss.qualcomm.com>
Co-developed-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Signed-off-by: Sayantan Chakraborty <sayantan.chakraborty@oss.qualcomm.com>
Reviewed-by: Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 125 +++++++++++++++++++++++++++++++++++
1 file changed, 125 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index ec1bfebed226..309ebe515814 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -6,6 +6,7 @@
#include <dt-bindings/clock/qcom,rpmcc.h>
#include <dt-bindings/clock/qcom,shikra-gcc.h>
#include <dt-bindings/interconnect/qcom,icc.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
#include <dt-bindings/dma/qcom-gpi.h>
#include <dt-bindings/interconnect/qcom,rpm-icc.h>
#include <dt-bindings/interconnect/qcom,shikra.h>
@@ -44,6 +45,14 @@ cpu0: cpu@0 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu1: cpu@100 {
@@ -54,6 +63,14 @@ cpu1: cpu@100 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu2: cpu@200 {
@@ -64,6 +81,14 @@ cpu2: cpu@200 {
next-level-cache = <&l3>;
capacity-dmips-mhz = <1024>;
dynamic-power-coefficient = <100>;
+ clocks = <&cpufreq_hw 0>;
+ qcom,freq-domain = <&cpufreq_hw 0>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu0_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
};
cpu3: cpu@300 {
@@ -74,6 +99,14 @@ cpu3: cpu@300 {
next-level-cache = <&l2_3>;
capacity-dmips-mhz = <1946>;
dynamic-power-coefficient = <489>;
+ clocks = <&cpufreq_hw 1>;
+ qcom,freq-domain = <&cpufreq_hw 1>;
+ #cooling-cells = <2>;
+ operating-points-v2 = <&cpu3_opp_table>;
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ACTIVE_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ACTIVE_TAG>,
+ <&epss_l3 MASTER_EPSS_L3_APPS
+ &epss_l3 SLAVE_EPSS_L3_SHARED>;
l2_3: l2-cache {
compatible = "cache";
@@ -132,6 +165,71 @@ memory@80000000 {
reg = <0x0 0x80000000 0x0 0x0>;
};
+ cpu0_opp_table: opp-table-cpu0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-768000000 {
+ opp-hz = /bits/ 64 <768000000>;
+ opp-peak-kBps = <1200000 17817600>;
+ };
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1094400000 {
+ opp-hz = /bits/ 64 <1094400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1612800000 {
+ opp-hz = /bits/ 64 <1612800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1804800000 {
+ opp-hz = /bits/ 64 <1804800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
+ cpu3_opp_table: opp-table-cpu3 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-1017600000 {
+ opp-hz = /bits/ 64 <1017600000>;
+ opp-peak-kBps = <2188000 25804800>;
+ };
+
+ opp-1190400000 {
+ opp-hz = /bits/ 64 <1190400000>;
+ opp-peak-kBps = <3072000 30105600>;
+ };
+
+ opp-1497600000 {
+ opp-hz = /bits/ 64 <1497600000>;
+ opp-peak-kBps = <4068000 38707200>;
+ };
+
+ opp-1708800000 {
+ opp-hz = /bits/ 64 <1708800000>;
+ opp-peak-kBps = <6220000 43008000>;
+ };
+
+ opp-1900800000 {
+ opp-hz = /bits/ 64 <1900800000>;
+ opp-peak-kBps = <7216000 43622400>;
+ };
+ };
+
pmu-a55 {
compatible = "arm,cortex-a55-pmu";
interrupts = <GIC_PPI 5 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
@@ -1820,6 +1918,33 @@ frame@f42d000 {
status = "disabled";
};
};
+
+ epss_l3: interconnect@fd90000 {
+ compatible = "qcom,shikra-epss-l3";
+ reg = <0x0 0x0fd90000 0x0 0x1000>;
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+ #interconnect-cells = <1>;
+ };
+
+ cpufreq_hw: cpufreq@fd91000 {
+ compatible = "qcom,shikra-epss";
+ reg = <0x0 0x0fd91000 0x0 0x1000>,
+ <0x0 0x0fd92000 0x0 0x1000>;
+ reg-names = "freq-domain0",
+ "freq-domain1";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>, <&gcc GPLL0>;
+ clock-names = "xo", "alternate";
+
+ interrupts = <GIC_SPI 30 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 31 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "dcvsh-irq-0",
+ "dcvsh-irq-1";
+
+ #freq-domain-cells = <1>;
+ #clock-cells = <1>;
+ };
};
timer {
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v3 06/10] arm64: dts: qcom: shikra: Add SMP2P nodes
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (4 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 05/10] arm64: dts: qcom: shikra: Add cpufreq-hw, EPSS L3 interconnect and OPP tables Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-06 12:45 ` Dmitry Baryshkov
2026-06-01 12:55 ` [PATCH v3 07/10] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes Komal Bajaj
` (3 subsequent siblings)
9 siblings, 1 reply; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Vishnu Santhosh
From: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable
inter-processor signalling for remoteproc state management.
Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++++++
1 file changed, 69 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 309ebe515814..219c904fba29 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -413,6 +413,75 @@ lmcu_dtb_mem: lmcu-dtb@b4702000 {
};
};
+ smp2p-cdsp {
+ compatible = "qcom,smp2p";
+ qcom,smem = <94>, <432>;
+
+ interrupts = <GIC_SPI 263 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 6>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <5>;
+
+ cdsp_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ cdsp_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-lmcu {
+ compatible = "qcom,smp2p";
+ qcom,smem = <617>, <616>;
+
+ interrupts = <GIC_SPI 287 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 10>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <26>;
+
+ lmcu_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ lmcu_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
+ smp2p-mpss {
+ compatible = "qcom,smp2p";
+ qcom,smem = <435>, <428>;
+
+ interrupts = <GIC_SPI 70 IRQ_TYPE_EDGE_RISING 0>;
+
+ mboxes = <&apcs_glb 14>;
+
+ qcom,local-pid = <0>;
+ qcom,remote-pid = <1>;
+
+ modem_smp2p_out: master-kernel {
+ qcom,entry-name = "master-kernel";
+ #qcom,smem-state-cells = <1>;
+ };
+
+ modem_smp2p_in: slave-kernel {
+ qcom,entry-name = "slave-kernel";
+ interrupt-controller;
+ #interrupt-cells = <2>;
+ };
+ };
+
soc: soc@0 {
compatible = "simple-bus";
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 06/10] arm64: dts: qcom: shikra: Add SMP2P nodes
2026-06-01 12:55 ` [PATCH v3 06/10] arm64: dts: qcom: shikra: Add SMP2P nodes Komal Bajaj
@ 2026-06-06 12:45 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2026-06-06 12:45 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Vishnu Santhosh
On Mon, Jun 01, 2026 at 06:25:08PM +0530, Komal Bajaj wrote:
> From: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
>
> Add SMP2P nodes for the cdsp, modem and lmcu subsystems to enable
> inter-processor signalling for remoteproc state management.
>
> Signed-off-by: Vishnu Santhosh <vishnu.santhosh@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra.dtsi | 69 ++++++++++++++++++++++++++++++++++++
> 1 file changed, 69 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 07/10] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (5 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 06/10] arm64: dts: qcom: shikra: Add SMP2P nodes Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards Komal Bajaj
` (2 subsequent siblings)
9 siblings, 0 replies; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Add nodes for remoteproc PAS loader for CDSP, LPAICP, MPSS subsystem.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 164 +++++++++++++++++++++++++++++++++++
1 file changed, 164 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 219c904fba29..445dd8bb7269 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -1798,6 +1798,170 @@ &clk_virt SLAVE_QUP_CORE_0 RPM_ALWAYS_TAG>,
};
};
+ remoteproc_mpss: remoteproc@6080000 {
+ compatible = "qcom,shikra-mpss-pas";
+ reg = <0x0 0x06080000 0x0 0x100>;
+
+ interrupts-extended = <&intc GIC_SPI 307 IRQ_TYPE_EDGE_RISING 0>,
+ <&modem_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&modem_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&mpss_wlan_mem>;
+
+ qcom,smem-states = <&modem_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 68 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 12>;
+ qcom,remote-pid = <1>;
+ label = "mpss";
+ };
+ };
+
+ remoteproc_cdsp: remoteproc@b300000 {
+ compatible = "qcom,shikra-cdsp-pas";
+ reg = <0x0 0x0b300000 0x0 0x100000>;
+
+ interrupts-extended = <&intc GIC_SPI 265 IRQ_TYPE_EDGE_RISING 0>,
+ <&cdsp_smp2p_in 0 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 1 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 2 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 3 IRQ_TYPE_EDGE_RISING>,
+ <&cdsp_smp2p_in 7 IRQ_TYPE_EDGE_RISING>;
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack",
+ "shutdown-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ interconnects = <&mem_noc MASTER_AMPSS_M0 RPM_ALWAYS_TAG
+ &mc_virt SLAVE_EBI_CH0 RPM_ALWAYS_TAG>;
+
+ power-domains = <&rpmpd RPMHPD_CX>;
+
+ memory-region = <&cdsp_mem>;
+
+ qcom,smem-states = <&cdsp_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 261 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 4>;
+ qcom,remote-pid = <5>;
+ label = "cdsp";
+
+ fastrpc {
+ compatible = "qcom,fastrpc";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ label = "cdsp";
+ qcom,glink-channels = "fastrpcglink-apps-dsp";
+
+ compute-cb@1 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <1>;
+ iommus = <&apps_smmu 0x0201 0x0000>;
+ };
+
+ compute-cb@2 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <2>;
+ iommus = <&apps_smmu 0x0202 0x0000>;
+ };
+
+ compute-cb@3 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <3>;
+ iommus = <&apps_smmu 0x0203 0x0000>;
+ };
+
+ compute-cb@4 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <4>;
+ iommus = <&apps_smmu 0x0204 0x0000>;
+ };
+
+ compute-cb@5 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <5>;
+ iommus = <&apps_smmu 0x0205 0x0000>;
+ };
+
+ compute-cb@6 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <6>;
+ iommus = <&apps_smmu 0x0206 0x0000>;
+ };
+
+ compute-cb@9 {
+ compatible = "qcom,fastrpc-compute-cb";
+ reg = <9>;
+ iommus = <&apps_smmu 0x0209 0x0000>;
+ };
+ };
+ };
+ };
+
+ remoteproc_lpaicp: remoteproc@b800000 {
+ compatible = "qcom,shikra-lpaicp-pas";
+ reg = <0x0 0x0b800000 0x0 0x200000>;
+
+ interrupts-extended = <&intc GIC_SPI 257 IRQ_TYPE_EDGE_RISING 0>,
+ <&lmcu_smp2p_in 0 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 1 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 2 IRQ_TYPE_NONE>,
+ <&lmcu_smp2p_in 3 IRQ_TYPE_NONE>;
+
+ interrupt-names = "wdog",
+ "fatal",
+ "ready",
+ "handover",
+ "stop-ack";
+
+ clocks = <&rpmcc RPM_SMD_XO_CLK_SRC>;
+ clock-names = "xo";
+
+ memory-region = <&lmcu_mem &lmcu_dtb_mem>;
+
+ qcom,smem-states = <&lmcu_smp2p_out 0>;
+ qcom,smem-state-names = "stop";
+
+ status = "disabled";
+
+ glink-edge {
+ interrupts = <GIC_SPI 286 IRQ_TYPE_EDGE_RISING 0>;
+ mboxes = <&apcs_glb 9>;
+ qcom,remote-pid = <26>;
+ label = "lpaicp";
+ };
+ };
+
sram@c11e000 {
compatible = "qcom,shikra-imem", "mmio-sram";
reg = <0x0 0x0c11e000 0x0 0x1000>;
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (6 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 07/10] arm64: dts: qcom: shikra: Add CDSP, LPAICP, MPSS remoteproc PAS nodes Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-06 12:32 ` Dmitry Baryshkov
2026-06-01 12:55 ` [PATCH v3 09/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones Komal Bajaj
2026-06-01 12:55 ` [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards Komal Bajaj
9 siblings, 1 reply; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Bibek Kumar Patro
From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and
IQS EVK board.
Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
3 files changed, 57 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index 0a52ab9b7a4c..b112b21b1d79 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index b3f19a64d7ae..e62ba5aef71f 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm4125_l20>;
vqmmc-supply = <&pm4125_l14>;
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 3003a47bd759..727809430fd1 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -23,6 +23,25 @@ chosen {
};
};
+&remoteproc_cdsp {
+ firmware-name = "qcom/shikra/cdsp.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_lpaicp {
+ firmware-name = "qcom/shikra/lpaicp.mbn",
+ "qcom/shikra/lpaicp_dtb.mbn";
+
+ status = "okay";
+};
+
+&remoteproc_mpss {
+ firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
+
+ status = "okay";
+};
+
&sdhc_1 {
vmmc-supply = <&pm8150_l17>;
vqmmc-supply = <&pm8150_s4>;
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
2026-06-01 12:55 ` [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards Komal Bajaj
@ 2026-06-06 12:32 ` Dmitry Baryshkov
2026-06-08 12:54 ` Komal Bajaj
0 siblings, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2026-06-06 12:32 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Bibek Kumar Patro
On Mon, Jun 01, 2026 at 06:25:10PM +0530, Komal Bajaj wrote:
> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>
> Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and
> IQS EVK board.
>
> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
> 3 files changed, 57 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> index 0a52ab9b7a4c..b112b21b1d79 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> @@ -23,6 +23,25 @@ chosen {
> };
> };
>
> +&remoteproc_cdsp {
> + firmware-name = "qcom/shikra/cdsp.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_lpaicp {
> + firmware-name = "qcom/shikra/lpaicp.mbn",
> + "qcom/shikra/lpaicp_dtb.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_mpss {
> + firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
qcom/shikra/qdsp6sw.mbn
> +
> + status = "okay";
> +};
> +
> &sdhc_1 {
> vmmc-supply = <&pm4125_l20>;
> vqmmc-supply = <&pm4125_l14>;
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> index b3f19a64d7ae..e62ba5aef71f 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> @@ -23,6 +23,25 @@ chosen {
> };
> };
>
> +&remoteproc_cdsp {
> + firmware-name = "qcom/shikra/cdsp.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_lpaicp {
> + firmware-name = "qcom/shikra/lpaicp.mbn",
> + "qcom/shikra/lpaicp_dtb.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_mpss {
> + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
qcom/shikra/qdsp6sw_nm.mbn
> +
> + status = "okay";
> +};
> +
> &sdhc_1 {
> vmmc-supply = <&pm4125_l20>;
> vqmmc-supply = <&pm4125_l14>;
> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> index 3003a47bd759..727809430fd1 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> @@ -23,6 +23,25 @@ chosen {
> };
> };
>
> +&remoteproc_cdsp {
> + firmware-name = "qcom/shikra/cdsp.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_lpaicp {
> + firmware-name = "qcom/shikra/lpaicp.mbn",
> + "qcom/shikra/lpaicp_dtb.mbn";
> +
> + status = "okay";
> +};
> +
> +&remoteproc_mpss {
> + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
qcom/shikra/qdsp6sw_nm.mbn
> +
> + status = "okay";
> +};
> +
> &sdhc_1 {
> vmmc-supply = <&pm8150_l17>;
> vqmmc-supply = <&pm8150_s4>;
>
> --
> 2.34.1
>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards
2026-06-06 12:32 ` Dmitry Baryshkov
@ 2026-06-08 12:54 ` Komal Bajaj
0 siblings, 0 replies; 23+ messages in thread
From: Komal Bajaj @ 2026-06-08 12:54 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Bibek Kumar Patro
On 6/6/2026 6:02 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 01, 2026 at 06:25:10PM +0530, Komal Bajaj wrote:
>> From: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>>
>> Enable CDSP, LPAICP and MPSS for Qualcomm's Shikra CQM, CQS and
>> IQS EVK board.
>>
>> Signed-off-by: Bibek Kumar Patro <bibek.patro@oss.qualcomm.com>
>> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 19 +++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 19 +++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 19 +++++++++++++++++++
>> 3 files changed, 57 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> index 0a52ab9b7a4c..b112b21b1d79 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> @@ -23,6 +23,25 @@ chosen {
>> };
>> };
>>
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/shikra/cdsp.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_lpaicp {
>> + firmware-name = "qcom/shikra/lpaicp.mbn",
>> + "qcom/shikra/lpaicp_dtb.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/shikra/cqm/qdsp6sw.mbn";
> qcom/shikra/qdsp6sw.mbn
>
>> +
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> vmmc-supply = <&pm4125_l20>;
>> vqmmc-supply = <&pm4125_l14>;
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> index b3f19a64d7ae..e62ba5aef71f 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> @@ -23,6 +23,25 @@ chosen {
>> };
>> };
>>
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/shikra/cdsp.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_lpaicp {
>> + firmware-name = "qcom/shikra/lpaicp.mbn",
>> + "qcom/shikra/lpaicp_dtb.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
> qcom/shikra/qdsp6sw_nm.mbn
We cannot change the firmware name, as our vendor builds and internal
tooling depend on the same naming convention for all three Shikra
variants. This is also why the binaries are placed under different paths.
Thanks
Komal
>
>> +
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> vmmc-supply = <&pm4125_l20>;
>> vqmmc-supply = <&pm4125_l14>;
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> index 3003a47bd759..727809430fd1 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> @@ -23,6 +23,25 @@ chosen {
>> };
>> };
>>
>> +&remoteproc_cdsp {
>> + firmware-name = "qcom/shikra/cdsp.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_lpaicp {
>> + firmware-name = "qcom/shikra/lpaicp.mbn",
>> + "qcom/shikra/lpaicp_dtb.mbn";
>> +
>> + status = "okay";
>> +};
>> +
>> +&remoteproc_mpss {
>> + firmware-name = "qcom/shikra/cqs/qdsp6sw.mbn";
> qcom/shikra/qdsp6sw_nm.mbn
>
>> +
>> + status = "okay";
>> +};
>> +
>> &sdhc_1 {
>> vmmc-supply = <&pm8150_l17>;
>> vqmmc-supply = <&pm8150_s4>;
>>
>> --
>> 2.34.1
>>
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 09/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (7 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 08/10] arm64: dts: qcom: shikra: Enable CDSP, LPAICP and MPSS on EVK boards Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-06 12:41 ` Dmitry Baryshkov
2026-06-01 12:55 ` [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards Komal Bajaj
9 siblings, 1 reply; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Gaurav Kohli
From: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
The shikra includes one TSENS instance, with a total of 14 thermal
sensors distributed across various locations on the SoC.
The TSENS max/reset threshold is configured to 120°C in the hardware.
Enable all TSENS instances, and define the thermal zones with a hot trip
at 110°C and critical trip at 115°C.
Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++++++++++
1 file changed, 267 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index 445dd8bb7269..c1f25ce89bb1 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -12,6 +12,7 @@
#include <dt-bindings/interconnect/qcom,shikra.h>
#include <dt-bindings/interrupt-controller/arm-gic.h>
#include <dt-bindings/power/qcom-rpmpd.h>
+#include <dt-bindings/thermal/thermal.h>
/ {
interrupt-parent = <&intc>;
@@ -983,6 +984,18 @@ spmi_bus: spmi@1c40000 {
qcom,ee = <0>;
};
+ tsens0: thermal-sensor@4411000 {
+ compatible = "qcom,shikra-tsens", "qcom,tsens-v2";
+ reg = <0x0 0x04411000 0x0 0x1000>,
+ <0x0 0x04410000 0x0 0x1000>;
+ interrupts = <GIC_SPI 275 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 190 IRQ_TYPE_LEVEL_HIGH 0>;
+ interrupt-names = "uplow",
+ "critical";
+ #qcom,sensors = <14>;
+ #thermal-sensor-cells = <1>;
+ };
+
rpm_msg_ram: sram@45f0000 {
compatible = "qcom,rpm-msg-ram", "mmio-sram";
reg = <0x0 0x045f0000 0x0 0x7000>;
@@ -2180,6 +2193,260 @@ cpufreq_hw: cpufreq@fd91000 {
};
};
+ thermal_zones: thermal-zones {
+ aoss0-thermal {
+ thermal-sensors = <&tsens0 0>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ aoss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-0-thermal {
+ thermal-sensors = <&tsens0 1>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu00-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-1-thermal {
+ thermal-sensors = <&tsens0 2>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu01-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-0-thermal {
+ thermal-sensors = <&tsens0 3>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu10-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-1-1-thermal {
+ thermal-sensors = <&tsens0 4>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu11-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss0-thermal {
+ thermal-sensors = <&tsens0 5>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ gpuss-thermal {
+ thermal-sensors = <&tsens0 6>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ gpuss-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ nsp-thermal {
+ thermal-sensors = <&tsens0 7>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ nsp-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss0-thermal {
+ thermal-sensors = <&tsens0 8>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss0-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ mdmss1-thermal {
+ thermal-sensors = <&tsens0 9>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ mdmss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ camera-thermal {
+ thermal-sensors = <&tsens0 10>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ camera-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ video-thermal {
+ thermal-sensors = <&tsens0 11>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ video-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpu-0-2-thermal {
+ thermal-sensors = <&tsens0 12>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpu02-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+
+ cpuss1-thermal {
+ thermal-sensors = <&tsens0 13>;
+
+ trips {
+ trip-point0 {
+ temperature = <110000>;
+ hysteresis = <5000>;
+ type = "hot";
+ };
+
+ cpuss1-critical {
+ temperature = <115000>;
+ hysteresis = <0>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 09/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones
2026-06-01 12:55 ` [PATCH v3 09/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones Komal Bajaj
@ 2026-06-06 12:41 ` Dmitry Baryshkov
0 siblings, 0 replies; 23+ messages in thread
From: Dmitry Baryshkov @ 2026-06-06 12:41 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Gaurav Kohli
On Mon, Jun 01, 2026 at 06:25:11PM +0530, Komal Bajaj wrote:
> From: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
>
> The shikra includes one TSENS instance, with a total of 14 thermal
> sensors distributed across various locations on the SoC.
>
> The TSENS max/reset threshold is configured to 120°C in the hardware.
> Enable all TSENS instances, and define the thermal zones with a hot trip
> at 110°C and critical trip at 115°C.
>
> Signed-off-by: Gaurav Kohli <gaurav.kohli@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra.dtsi | 267 +++++++++++++++++++++++++++++++++++
> 1 file changed, 267 insertions(+)
>
Reviewed-by: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread
* [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
2026-06-01 12:55 [PATCH v3 00/10] arm64: dts: qcom: Extend Shikra device tree with peripheral and subsystem support Komal Bajaj
` (8 preceding siblings ...)
2026-06-01 12:55 ` [PATCH v3 09/10] arm64: dts: qcom: shikra: Enable TSENS and thermal zones Komal Bajaj
@ 2026-06-01 12:55 ` Komal Bajaj
2026-06-06 12:45 ` Dmitry Baryshkov
2026-06-06 12:57 ` Loic Poulain
9 siblings, 2 replies; 23+ messages in thread
From: Komal Bajaj @ 2026-06-01 12:55 UTC (permalink / raw)
To: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio
Cc: linux-arm-msm, dmaengine, devicetree, linux-kernel, linux-pm,
Komal Bajaj, Yepuri Siddu, Miaoqing Pan
Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
EVK boards using the WCN3988 combo chip.
For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
board-specific regulator supplies across CQM, CQS and IQS Shikra
EVK boards.
For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
with register space, interrupts, IOMMU configuration and reserved
memory. The node is kept disabled by default and enabled per-board
with the appropriate PMIC supply connections and calibration variant
selection.
Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
---
arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
5 files changed, 223 insertions(+)
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
index b112b21b1d79..c2ed0396533a 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
@@ -16,11 +16,48 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&remoteproc_cdsp {
@@ -57,3 +94,25 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "cq2390";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
index e62ba5aef71f..3bfd0050064f 100644
--- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
@@ -16,11 +16,48 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ vddio-supply = <&pm4125_l7>;
+ vddxo-supply = <&pm4125_l13>;
+ vddrf-supply = <&pm4125_l10>;
+ vddch0-supply = <&pm4125_l22>;
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&remoteproc_cdsp {
@@ -57,3 +94,25 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm4125_l7>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "cq2390";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
index 8b03d4eafa6d..a79f44aff968 100644
--- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
@@ -8,7 +8,22 @@ &qupv3_0 {
status = "okay";
};
+&tlmm {
+ sw_ctrl_default: sw-ctrl-default-state {
+ pins = "gpio88";
+ function = "gpio";
+ bias-pull-down;
+ };
+};
+
&uart0 {
status = "okay";
};
+&uart8 {
+ bluetooth {
+ compatible = "qcom,wcn3988-bt";
+ max-speed = <3200000>;
+ };
+};
+
diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
index 727809430fd1..95bd797d009d 100644
--- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
+++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
@@ -16,11 +16,56 @@ / {
aliases {
mmc0 = &sdhc_1;
serial0 = &uart0;
+ serial1 = &uart8;
};
chosen {
stdout-path = "serial0:115200n8";
};
+
+ vreg_wcn_3p3: regulator-wcn-3p3 {
+ compatible = "regulator-fixed";
+ regulator-name = "wcn_3p3";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ };
+
+ wcn3988-pmu {
+ compatible = "qcom,wcn3988-pmu";
+
+ pinctrl-0 = <&sw_ctrl_default>;
+ pinctrl-names = "default";
+
+ vddio-supply = <&pm8150_s4>;
+ vddxo-supply = <&pm8150_l12>;
+ vddrf-supply = <&pm8150_l8>;
+ vddch0-supply = <&vreg_wcn_3p3>;
+
+ swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
+
+ regulators {
+ vreg_pmu_io: ldo0 {
+ regulator-name = "vreg_pmu_io";
+ };
+
+ vreg_pmu_xo: ldo1 {
+ regulator-name = "vreg_pmu_xo";
+ };
+
+ vreg_pmu_rf: ldo2 {
+ regulator-name = "vreg_pmu_rf";
+ };
+
+ vreg_pmu_ch0: ldo3 {
+ regulator-name = "vreg_pmu_ch0";
+ };
+
+ vreg_pmu_ch1: ldo4 {
+ regulator-name = "vreg_pmu_ch1";
+ };
+ };
+ };
};
&remoteproc_cdsp {
@@ -57,3 +102,25 @@ &sdhc_1 {
status = "okay";
};
+
+&uart8 {
+ status = "okay";
+
+ bluetooth {
+ vddio-supply = <&vreg_pmu_io>;
+ vddxo-supply = <&vreg_pmu_xo>;
+ vddrf-supply = <&vreg_pmu_rf>;
+ vddch0-supply = <&vreg_pmu_ch0>;
+ };
+};
+
+&wifi {
+ vdd-0.8-cx-mx-supply = <&pm8150_s4>;
+ vdd-1.8-xo-supply = <&vreg_pmu_xo>;
+ vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
+ vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
+ qcom,calibration-variant = "Shikra_EVK";
+ firmware-name = "cq2390";
+
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
index c1f25ce89bb1..6bac6ebac8da 100644
--- a/arch/arm64/boot/dts/qcom/shikra.dtsi
+++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
@@ -2064,6 +2064,29 @@ apps_smmu: iommu@c600000 {
<GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
};
+ wifi: wifi@c800000 {
+ compatible = "qcom,wcn3990-wifi";
+ reg = <0x0 0x0c800000 0x0 0x800000>;
+ reg-names = "membase";
+ memory-region = <&wlan_mem>;
+ interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&apps_smmu 0x1a0 0x1>;
+ qcom,msa-fixed-perm;
+
+ status = "disabled";
+ };
+
intc: interrupt-controller@f200000 {
compatible = "arm,gic-v3";
reg = <0x0 0xf200000 0x0 0x10000>,
--
2.34.1
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
2026-06-01 12:55 ` [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards Komal Bajaj
@ 2026-06-06 12:45 ` Dmitry Baryshkov
2026-06-08 13:00 ` Komal Bajaj
2026-06-06 12:57 ` Loic Poulain
1 sibling, 1 reply; 23+ messages in thread
From: Dmitry Baryshkov @ 2026-06-06 12:45 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Yepuri Siddu, Miaoqing Pan
On Mon, Jun 01, 2026 at 06:25:12PM +0530, Komal Bajaj wrote:
> Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
> EVK boards using the WCN3988 combo chip.
>
> For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
> board-specific regulator supplies across CQM, CQS and IQS Shikra
> EVK boards.
>
> For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
> with register space, interrupts, IOMMU configuration and reserved
> memory. The node is kept disabled by default and enabled per-board
> with the appropriate PMIC supply connections and calibration variant
> selection.
>
> Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
> Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
> Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
> Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
> 5 files changed, 223 insertions(+)
>
> +
> +&wifi {
> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> + qcom,calibration-variant = "Shikra_EVK";
> + firmware-name = "cq2390";
firmware-name = "shikra";
> +
> + status = "okay";
> +};
> +
[...]
> +&wifi {
> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> + qcom,calibration-variant = "Shikra_EVK";
I hope this means that calibration files are common across the boards.
> + firmware-name = "cq2390";
firmware-name = "shikra";
> +
> + status = "okay";
> +};
[...]
> +
> +&wifi {
> + vdd-0.8-cx-mx-supply = <&pm8150_s4>;
> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> + qcom,calibration-variant = "Shikra_EVK";
> + firmware-name = "cq2390";
firmware-name = "shikra";
> +
> + status = "okay";
> +};
--
With best wishes
Dmitry
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
2026-06-06 12:45 ` Dmitry Baryshkov
@ 2026-06-08 13:00 ` Komal Bajaj
0 siblings, 0 replies; 23+ messages in thread
From: Komal Bajaj @ 2026-06-08 13:00 UTC (permalink / raw)
To: Dmitry Baryshkov
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Yepuri Siddu, Miaoqing Pan
On 6/6/2026 6:15 PM, Dmitry Baryshkov wrote:
> On Mon, Jun 01, 2026 at 06:25:12PM +0530, Komal Bajaj wrote:
>> Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
>> EVK boards using the WCN3988 combo chip.
>>
>> For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
>> board-specific regulator supplies across CQM, CQS and IQS Shikra
>> EVK boards.
>>
>> For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
>> with register space, interrupts, IOMMU configuration and reserved
>> memory. The node is kept disabled by default and enabled per-board
>> with the appropriate PMIC supply connections and calibration variant
>> selection.
>>
>> Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
>> Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
>> Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
>> Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
>> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
>> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
>> 5 files changed, 223 insertions(+)
>>
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
> firmware-name = "shikra";
ACK. I will update the name in next revision.
>
>> +
>> + status = "okay";
>> +};
>> +
> [...]
>
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
> I hope this means that calibration files are common across the boards.
Yes, it is.
Thanks
Komal
>
>> + firmware-name = "cq2390";
> firmware-name = "shikra";
>
>> +
>> + status = "okay";
>> +};
>
> [...]
>
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm8150_s4>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
> firmware-name = "shikra";
>> +
>> + status = "okay";
>> +};
^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
2026-06-01 12:55 ` [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards Komal Bajaj
2026-06-06 12:45 ` Dmitry Baryshkov
@ 2026-06-06 12:57 ` Loic Poulain
2026-06-08 2:26 ` Miaoqing Pan
1 sibling, 1 reply; 23+ messages in thread
From: Loic Poulain @ 2026-06-06 12:57 UTC (permalink / raw)
To: Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Yepuri Siddu, Miaoqing Pan
On Mon, Jun 1, 2026 at 2:57 PM Komal Bajaj <komal.bajaj@oss.qualcomm.com> wrote:
>
> Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
> EVK boards using the WCN3988 combo chip.
>
> For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
> board-specific regulator supplies across CQM, CQS and IQS Shikra
> EVK boards.
>
> For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
> with register space, interrupts, IOMMU configuration and reserved
> memory. The node is kept disabled by default and enabled per-board
> with the appropriate PMIC supply connections and calibration variant
> selection.
>
> Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
> Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
> Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
> Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> ---
> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
> arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
> 5 files changed, 223 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> index b112b21b1d79..c2ed0396533a 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> @@ -16,11 +16,48 @@ / {
> aliases {
> mmc0 = &sdhc_1;
> serial0 = &uart0;
> + serial1 = &uart8;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + wcn3988-pmu {
> + compatible = "qcom,wcn3988-pmu";
> +
> + pinctrl-0 = <&sw_ctrl_default>;
> + pinctrl-names = "default";
> +
> + vddio-supply = <&pm4125_l7>;
> + vddxo-supply = <&pm4125_l13>;
> + vddrf-supply = <&pm4125_l10>;
> + vddch0-supply = <&pm4125_l22>;
> +
> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> +
> + regulators {
> + vreg_pmu_io: ldo0 {
> + regulator-name = "vreg_pmu_io";
> + };
> +
> + vreg_pmu_xo: ldo1 {
> + regulator-name = "vreg_pmu_xo";
> + };
> +
> + vreg_pmu_rf: ldo2 {
> + regulator-name = "vreg_pmu_rf";
> + };
> +
> + vreg_pmu_ch0: ldo3 {
> + regulator-name = "vreg_pmu_ch0";
> + };
> +
> + vreg_pmu_ch1: ldo4 {
> + regulator-name = "vreg_pmu_ch1";
> + };
> + };
> + };
> };
>
> &remoteproc_cdsp {
> @@ -57,3 +94,25 @@ &sdhc_1 {
>
> status = "okay";
> };
> +
> +&uart8 {
> + status = "okay";
> +
> + bluetooth {
> + vddio-supply = <&vreg_pmu_io>;
> + vddxo-supply = <&vreg_pmu_xo>;
> + vddrf-supply = <&vreg_pmu_rf>;
> + vddch0-supply = <&vreg_pmu_ch0>;
> + };
> +};
> +
> +&wifi {
> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> + qcom,calibration-variant = "Shikra_EVK";
> + firmware-name = "cq2390";
> +
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> index e62ba5aef71f..3bfd0050064f 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> @@ -16,11 +16,48 @@ / {
> aliases {
> mmc0 = &sdhc_1;
> serial0 = &uart0;
> + serial1 = &uart8;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + wcn3988-pmu {
> + compatible = "qcom,wcn3988-pmu";
> +
> + pinctrl-0 = <&sw_ctrl_default>;
> + pinctrl-names = "default";
> +
> + vddio-supply = <&pm4125_l7>;
> + vddxo-supply = <&pm4125_l13>;
> + vddrf-supply = <&pm4125_l10>;
> + vddch0-supply = <&pm4125_l22>;
> +
> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> +
> + regulators {
> + vreg_pmu_io: ldo0 {
> + regulator-name = "vreg_pmu_io";
> + };
> +
> + vreg_pmu_xo: ldo1 {
> + regulator-name = "vreg_pmu_xo";
> + };
> +
> + vreg_pmu_rf: ldo2 {
> + regulator-name = "vreg_pmu_rf";
> + };
> +
> + vreg_pmu_ch0: ldo3 {
> + regulator-name = "vreg_pmu_ch0";
> + };
> +
> + vreg_pmu_ch1: ldo4 {
> + regulator-name = "vreg_pmu_ch1";
> + };
> + };
> + };
> };
>
> &remoteproc_cdsp {
> @@ -57,3 +94,25 @@ &sdhc_1 {
>
> status = "okay";
> };
> +
> +&uart8 {
> + status = "okay";
> +
> + bluetooth {
> + vddio-supply = <&vreg_pmu_io>;
> + vddxo-supply = <&vreg_pmu_xo>;
> + vddrf-supply = <&vreg_pmu_rf>;
> + vddch0-supply = <&vreg_pmu_ch0>;
> + };
> +};
> +
> +&wifi {
> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> + qcom,calibration-variant = "Shikra_EVK";
> + firmware-name = "cq2390";
> +
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> index 8b03d4eafa6d..a79f44aff968 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> @@ -8,7 +8,22 @@ &qupv3_0 {
> status = "okay";
> };
>
> +&tlmm {
> + sw_ctrl_default: sw-ctrl-default-state {
> + pins = "gpio88";
> + function = "gpio";
> + bias-pull-down;
> + };
> +};
> +
> &uart0 {
> status = "okay";
> };
>
> +&uart8 {
> + bluetooth {
> + compatible = "qcom,wcn3988-bt";
> + max-speed = <3200000>;
> + };
> +};
> +
> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> index 727809430fd1..95bd797d009d 100644
> --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> @@ -16,11 +16,56 @@ / {
> aliases {
> mmc0 = &sdhc_1;
> serial0 = &uart0;
> + serial1 = &uart8;
> };
>
> chosen {
> stdout-path = "serial0:115200n8";
> };
> +
> + vreg_wcn_3p3: regulator-wcn-3p3 {
> + compatible = "regulator-fixed";
> + regulator-name = "wcn_3p3";
> + regulator-min-microvolt = <3300000>;
> + regulator-max-microvolt = <3300000>;
> + regulator-always-on;
> + };
> +
> + wcn3988-pmu {
> + compatible = "qcom,wcn3988-pmu";
> +
> + pinctrl-0 = <&sw_ctrl_default>;
> + pinctrl-names = "default";
> +
> + vddio-supply = <&pm8150_s4>;
> + vddxo-supply = <&pm8150_l12>;
> + vddrf-supply = <&pm8150_l8>;
> + vddch0-supply = <&vreg_wcn_3p3>;
> +
> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> +
> + regulators {
> + vreg_pmu_io: ldo0 {
> + regulator-name = "vreg_pmu_io";
> + };
> +
> + vreg_pmu_xo: ldo1 {
> + regulator-name = "vreg_pmu_xo";
> + };
> +
> + vreg_pmu_rf: ldo2 {
> + regulator-name = "vreg_pmu_rf";
> + };
> +
> + vreg_pmu_ch0: ldo3 {
> + regulator-name = "vreg_pmu_ch0";
> + };
> +
> + vreg_pmu_ch1: ldo4 {
> + regulator-name = "vreg_pmu_ch1";
> + };
> + };
> + };
> };
>
> &remoteproc_cdsp {
> @@ -57,3 +102,25 @@ &sdhc_1 {
>
> status = "okay";
> };
> +
> +&uart8 {
> + status = "okay";
> +
> + bluetooth {
> + vddio-supply = <&vreg_pmu_io>;
> + vddxo-supply = <&vreg_pmu_xo>;
> + vddrf-supply = <&vreg_pmu_rf>;
> + vddch0-supply = <&vreg_pmu_ch0>;
> + };
> +};
> +
> +&wifi {
> + vdd-0.8-cx-mx-supply = <&pm8150_s4>;
> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> + qcom,calibration-variant = "Shikra_EVK";
> + firmware-name = "cq2390";
Does the firmware differ from the one used on Agatti (QCM2290)?
> +
> + status = "okay";
> +};
> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
> index c1f25ce89bb1..6bac6ebac8da 100644
> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
> @@ -2064,6 +2064,29 @@ apps_smmu: iommu@c600000 {
> <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
> };
>
> + wifi: wifi@c800000 {
> + compatible = "qcom,wcn3990-wifi";
> + reg = <0x0 0x0c800000 0x0 0x800000>;
> + reg-names = "membase";
> + memory-region = <&wlan_mem>;
> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&apps_smmu 0x1a0 0x1>;
> + qcom,msa-fixed-perm;
> +
> + status = "disabled";
> + };
> +
> intc: interrupt-controller@f200000 {
> compatible = "arm,gic-v3";
> reg = <0x0 0xf200000 0x0 0x10000>,
>
> --
> 2.34.1
>
>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
2026-06-06 12:57 ` Loic Poulain
@ 2026-06-08 2:26 ` Miaoqing Pan
2026-06-08 8:22 ` Loic Poulain
0 siblings, 1 reply; 23+ messages in thread
From: Miaoqing Pan @ 2026-06-08 2:26 UTC (permalink / raw)
To: Loic Poulain, Komal Bajaj
Cc: Vinod Koul, Frank Li, Rob Herring, Krzysztof Kozlowski,
Conor Dooley, Krzysztof Kozlowski, Georgi Djakov,
Bjorn Andersson, Konrad Dybcio, linux-arm-msm, dmaengine,
devicetree, linux-kernel, linux-pm, Yepuri Siddu
On 6/6/2026 8:57 PM, Loic Poulain wrote:
> On Mon, Jun 1, 2026 at 2:57 PM Komal Bajaj <komal.bajaj@oss.qualcomm.com> wrote:
>> Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
>> EVK boards using the WCN3988 combo chip.
>>
>> For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
>> board-specific regulator supplies across CQM, CQS and IQS Shikra
>> EVK boards.
>>
>> For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
>> with register space, interrupts, IOMMU configuration and reserved
>> memory. The node is kept disabled by default and enabled per-board
>> with the appropriate PMIC supply connections and calibration variant
>> selection.
>>
>> Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
>> Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
>> Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
>> Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
>> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
>> ---
>> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
>> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
>> arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
>> 5 files changed, 223 insertions(+)
>>
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> index b112b21b1d79..c2ed0396533a 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
>> @@ -16,11 +16,48 @@ / {
>> aliases {
>> mmc0 = &sdhc_1;
>> serial0 = &uart0;
>> + serial1 = &uart8;
>> };
>>
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + wcn3988-pmu {
>> + compatible = "qcom,wcn3988-pmu";
>> +
>> + pinctrl-0 = <&sw_ctrl_default>;
>> + pinctrl-names = "default";
>> +
>> + vddio-supply = <&pm4125_l7>;
>> + vddxo-supply = <&pm4125_l13>;
>> + vddrf-supply = <&pm4125_l10>;
>> + vddch0-supply = <&pm4125_l22>;
>> +
>> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
>> +
>> + regulators {
>> + vreg_pmu_io: ldo0 {
>> + regulator-name = "vreg_pmu_io";
>> + };
>> +
>> + vreg_pmu_xo: ldo1 {
>> + regulator-name = "vreg_pmu_xo";
>> + };
>> +
>> + vreg_pmu_rf: ldo2 {
>> + regulator-name = "vreg_pmu_rf";
>> + };
>> +
>> + vreg_pmu_ch0: ldo3 {
>> + regulator-name = "vreg_pmu_ch0";
>> + };
>> +
>> + vreg_pmu_ch1: ldo4 {
>> + regulator-name = "vreg_pmu_ch1";
>> + };
>> + };
>> + };
>> };
>>
>> &remoteproc_cdsp {
>> @@ -57,3 +94,25 @@ &sdhc_1 {
>>
>> status = "okay";
>> };
>> +
>> +&uart8 {
>> + status = "okay";
>> +
>> + bluetooth {
>> + vddio-supply = <&vreg_pmu_io>;
>> + vddxo-supply = <&vreg_pmu_xo>;
>> + vddrf-supply = <&vreg_pmu_rf>;
>> + vddch0-supply = <&vreg_pmu_ch0>;
>> + };
>> +};
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
>> +
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> index e62ba5aef71f..3bfd0050064f 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
>> @@ -16,11 +16,48 @@ / {
>> aliases {
>> mmc0 = &sdhc_1;
>> serial0 = &uart0;
>> + serial1 = &uart8;
>> };
>>
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + wcn3988-pmu {
>> + compatible = "qcom,wcn3988-pmu";
>> +
>> + pinctrl-0 = <&sw_ctrl_default>;
>> + pinctrl-names = "default";
>> +
>> + vddio-supply = <&pm4125_l7>;
>> + vddxo-supply = <&pm4125_l13>;
>> + vddrf-supply = <&pm4125_l10>;
>> + vddch0-supply = <&pm4125_l22>;
>> +
>> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
>> +
>> + regulators {
>> + vreg_pmu_io: ldo0 {
>> + regulator-name = "vreg_pmu_io";
>> + };
>> +
>> + vreg_pmu_xo: ldo1 {
>> + regulator-name = "vreg_pmu_xo";
>> + };
>> +
>> + vreg_pmu_rf: ldo2 {
>> + regulator-name = "vreg_pmu_rf";
>> + };
>> +
>> + vreg_pmu_ch0: ldo3 {
>> + regulator-name = "vreg_pmu_ch0";
>> + };
>> +
>> + vreg_pmu_ch1: ldo4 {
>> + regulator-name = "vreg_pmu_ch1";
>> + };
>> + };
>> + };
>> };
>>
>> &remoteproc_cdsp {
>> @@ -57,3 +94,25 @@ &sdhc_1 {
>>
>> status = "okay";
>> };
>> +
>> +&uart8 {
>> + status = "okay";
>> +
>> + bluetooth {
>> + vddio-supply = <&vreg_pmu_io>;
>> + vddxo-supply = <&vreg_pmu_xo>;
>> + vddrf-supply = <&vreg_pmu_rf>;
>> + vddch0-supply = <&vreg_pmu_ch0>;
>> + };
>> +};
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
>> +
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
>> index 8b03d4eafa6d..a79f44aff968 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
>> @@ -8,7 +8,22 @@ &qupv3_0 {
>> status = "okay";
>> };
>>
>> +&tlmm {
>> + sw_ctrl_default: sw-ctrl-default-state {
>> + pins = "gpio88";
>> + function = "gpio";
>> + bias-pull-down;
>> + };
>> +};
>> +
>> &uart0 {
>> status = "okay";
>> };
>>
>> +&uart8 {
>> + bluetooth {
>> + compatible = "qcom,wcn3988-bt";
>> + max-speed = <3200000>;
>> + };
>> +};
>> +
>> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> index 727809430fd1..95bd797d009d 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
>> @@ -16,11 +16,56 @@ / {
>> aliases {
>> mmc0 = &sdhc_1;
>> serial0 = &uart0;
>> + serial1 = &uart8;
>> };
>>
>> chosen {
>> stdout-path = "serial0:115200n8";
>> };
>> +
>> + vreg_wcn_3p3: regulator-wcn-3p3 {
>> + compatible = "regulator-fixed";
>> + regulator-name = "wcn_3p3";
>> + regulator-min-microvolt = <3300000>;
>> + regulator-max-microvolt = <3300000>;
>> + regulator-always-on;
>> + };
>> +
>> + wcn3988-pmu {
>> + compatible = "qcom,wcn3988-pmu";
>> +
>> + pinctrl-0 = <&sw_ctrl_default>;
>> + pinctrl-names = "default";
>> +
>> + vddio-supply = <&pm8150_s4>;
>> + vddxo-supply = <&pm8150_l12>;
>> + vddrf-supply = <&pm8150_l8>;
>> + vddch0-supply = <&vreg_wcn_3p3>;
>> +
>> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
>> +
>> + regulators {
>> + vreg_pmu_io: ldo0 {
>> + regulator-name = "vreg_pmu_io";
>> + };
>> +
>> + vreg_pmu_xo: ldo1 {
>> + regulator-name = "vreg_pmu_xo";
>> + };
>> +
>> + vreg_pmu_rf: ldo2 {
>> + regulator-name = "vreg_pmu_rf";
>> + };
>> +
>> + vreg_pmu_ch0: ldo3 {
>> + regulator-name = "vreg_pmu_ch0";
>> + };
>> +
>> + vreg_pmu_ch1: ldo4 {
>> + regulator-name = "vreg_pmu_ch1";
>> + };
>> + };
>> + };
>> };
>>
>> &remoteproc_cdsp {
>> @@ -57,3 +102,25 @@ &sdhc_1 {
>>
>> status = "okay";
>> };
>> +
>> +&uart8 {
>> + status = "okay";
>> +
>> + bluetooth {
>> + vddio-supply = <&vreg_pmu_io>;
>> + vddxo-supply = <&vreg_pmu_xo>;
>> + vddrf-supply = <&vreg_pmu_rf>;
>> + vddch0-supply = <&vreg_pmu_ch0>;
>> + };
>> +};
>> +
>> +&wifi {
>> + vdd-0.8-cx-mx-supply = <&pm8150_s4>;
>> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
>> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
>> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
>> + qcom,calibration-variant = "Shikra_EVK";
>> + firmware-name = "cq2390";
> Does the firmware differ from the one used on Agatti (QCM2290)?
Yes, WCN3950 vs WCN3980.
>
>
>> +
>> + status = "okay";
>> +};
>> diff --git a/arch/arm64/boot/dts/qcom/shikra.dtsi b/arch/arm64/boot/dts/qcom/shikra.dtsi
>> index c1f25ce89bb1..6bac6ebac8da 100644
>> --- a/arch/arm64/boot/dts/qcom/shikra.dtsi
>> +++ b/arch/arm64/boot/dts/qcom/shikra.dtsi
>> @@ -2064,6 +2064,29 @@ apps_smmu: iommu@c600000 {
>> <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
>> };
>>
>> + wifi: wifi@c800000 {
>> + compatible = "qcom,wcn3990-wifi";
>> + reg = <0x0 0x0c800000 0x0 0x800000>;
>> + reg-names = "membase";
>> + memory-region = <&wlan_mem>;
>> + interrupts = <GIC_SPI 358 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 359 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 360 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 361 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 362 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 363 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 364 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 365 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 366 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 367 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 368 IRQ_TYPE_LEVEL_HIGH 0>,
>> + <GIC_SPI 369 IRQ_TYPE_LEVEL_HIGH 0>;
>> + iommus = <&apps_smmu 0x1a0 0x1>;
>> + qcom,msa-fixed-perm;
>> +
>> + status = "disabled";
>> + };
>> +
>> intc: interrupt-controller@f200000 {
>> compatible = "arm,gic-v3";
>> reg = <0x0 0xf200000 0x0 0x10000>,
>>
>> --
>> 2.34.1
>>
>>
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PATCH v3 10/10] arm64: dts: qcom: shikra: Enable Bluetooth and WiFi on EVK boards
2026-06-08 2:26 ` Miaoqing Pan
@ 2026-06-08 8:22 ` Loic Poulain
0 siblings, 0 replies; 23+ messages in thread
From: Loic Poulain @ 2026-06-08 8:22 UTC (permalink / raw)
To: Miaoqing Pan
Cc: Komal Bajaj, Vinod Koul, Frank Li, Rob Herring,
Krzysztof Kozlowski, Conor Dooley, Krzysztof Kozlowski,
Georgi Djakov, Bjorn Andersson, Konrad Dybcio, linux-arm-msm,
dmaengine, devicetree, linux-kernel, linux-pm, Yepuri Siddu
On Mon, Jun 8, 2026 at 4:26 AM Miaoqing Pan
<miaoqing.pan@oss.qualcomm.com> wrote:
>
>
>
> On 6/6/2026 8:57 PM, Loic Poulain wrote:
> > On Mon, Jun 1, 2026 at 2:57 PM Komal Bajaj <komal.bajaj@oss.qualcomm.com> wrote:
> >> Enable Bluetooth and WiFi connectivity on Shikra CQM, CQS and IQS
> >> EVK boards using the WCN3988 combo chip.
> >>
> >> For Bluetooth, enable uart8 and add WCN3988 Bluetooth node with
> >> board-specific regulator supplies across CQM, CQS and IQS Shikra
> >> EVK boards.
> >>
> >> For WiFi, introduce the wcn3990-wifi hardware node in shikra.dtsi
> >> with register space, interrupts, IOMMU configuration and reserved
> >> memory. The node is kept disabled by default and enabled per-board
> >> with the appropriate PMIC supply connections and calibration variant
> >> selection.
> >>
> >> Co-developed-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
> >> Signed-off-by: Yepuri Siddu <yepuri.siddu@oss.qualcomm.com>
> >> Co-developed-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
> >> Signed-off-by: Miaoqing Pan <miaoqing.pan@oss.qualcomm.com>
> >> Signed-off-by: Komal Bajaj <komal.bajaj@oss.qualcomm.com>
> >> ---
> >> arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts | 59 +++++++++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts | 59 +++++++++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/shikra-evk.dtsi | 15 +++++++
> >> arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts | 67 +++++++++++++++++++++++++++++
> >> arch/arm64/boot/dts/qcom/shikra.dtsi | 23 ++++++++++
> >> 5 files changed, 223 insertions(+)
> >>
> >> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> >> index b112b21b1d79..c2ed0396533a 100644
> >> --- a/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> >> +++ b/arch/arm64/boot/dts/qcom/shikra-cqm-evk.dts
> >> @@ -16,11 +16,48 @@ / {
> >> aliases {
> >> mmc0 = &sdhc_1;
> >> serial0 = &uart0;
> >> + serial1 = &uart8;
> >> };
> >>
> >> chosen {
> >> stdout-path = "serial0:115200n8";
> >> };
> >> +
> >> + wcn3988-pmu {
> >> + compatible = "qcom,wcn3988-pmu";
> >> +
> >> + pinctrl-0 = <&sw_ctrl_default>;
> >> + pinctrl-names = "default";
> >> +
> >> + vddio-supply = <&pm4125_l7>;
> >> + vddxo-supply = <&pm4125_l13>;
> >> + vddrf-supply = <&pm4125_l10>;
> >> + vddch0-supply = <&pm4125_l22>;
> >> +
> >> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> >> +
> >> + regulators {
> >> + vreg_pmu_io: ldo0 {
> >> + regulator-name = "vreg_pmu_io";
> >> + };
> >> +
> >> + vreg_pmu_xo: ldo1 {
> >> + regulator-name = "vreg_pmu_xo";
> >> + };
> >> +
> >> + vreg_pmu_rf: ldo2 {
> >> + regulator-name = "vreg_pmu_rf";
> >> + };
> >> +
> >> + vreg_pmu_ch0: ldo3 {
> >> + regulator-name = "vreg_pmu_ch0";
> >> + };
> >> +
> >> + vreg_pmu_ch1: ldo4 {
> >> + regulator-name = "vreg_pmu_ch1";
> >> + };
> >> + };
> >> + };
> >> };
> >>
> >> &remoteproc_cdsp {
> >> @@ -57,3 +94,25 @@ &sdhc_1 {
> >>
> >> status = "okay";
> >> };
> >> +
> >> +&uart8 {
> >> + status = "okay";
> >> +
> >> + bluetooth {
> >> + vddio-supply = <&vreg_pmu_io>;
> >> + vddxo-supply = <&vreg_pmu_xo>;
> >> + vddrf-supply = <&vreg_pmu_rf>;
> >> + vddch0-supply = <&vreg_pmu_ch0>;
> >> + };
> >> +};
> >> +
> >> +&wifi {
> >> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
> >> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> >> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> >> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> >> + qcom,calibration-variant = "Shikra_EVK";
> >> + firmware-name = "cq2390";
> >> +
> >> + status = "okay";
> >> +};
> >> diff --git a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> >> index e62ba5aef71f..3bfd0050064f 100644
> >> --- a/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> >> +++ b/arch/arm64/boot/dts/qcom/shikra-cqs-evk.dts
> >> @@ -16,11 +16,48 @@ / {
> >> aliases {
> >> mmc0 = &sdhc_1;
> >> serial0 = &uart0;
> >> + serial1 = &uart8;
> >> };
> >>
> >> chosen {
> >> stdout-path = "serial0:115200n8";
> >> };
> >> +
> >> + wcn3988-pmu {
> >> + compatible = "qcom,wcn3988-pmu";
> >> +
> >> + pinctrl-0 = <&sw_ctrl_default>;
> >> + pinctrl-names = "default";
> >> +
> >> + vddio-supply = <&pm4125_l7>;
> >> + vddxo-supply = <&pm4125_l13>;
> >> + vddrf-supply = <&pm4125_l10>;
> >> + vddch0-supply = <&pm4125_l22>;
> >> +
> >> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> >> +
> >> + regulators {
> >> + vreg_pmu_io: ldo0 {
> >> + regulator-name = "vreg_pmu_io";
> >> + };
> >> +
> >> + vreg_pmu_xo: ldo1 {
> >> + regulator-name = "vreg_pmu_xo";
> >> + };
> >> +
> >> + vreg_pmu_rf: ldo2 {
> >> + regulator-name = "vreg_pmu_rf";
> >> + };
> >> +
> >> + vreg_pmu_ch0: ldo3 {
> >> + regulator-name = "vreg_pmu_ch0";
> >> + };
> >> +
> >> + vreg_pmu_ch1: ldo4 {
> >> + regulator-name = "vreg_pmu_ch1";
> >> + };
> >> + };
> >> + };
> >> };
> >>
> >> &remoteproc_cdsp {
> >> @@ -57,3 +94,25 @@ &sdhc_1 {
> >>
> >> status = "okay";
> >> };
> >> +
> >> +&uart8 {
> >> + status = "okay";
> >> +
> >> + bluetooth {
> >> + vddio-supply = <&vreg_pmu_io>;
> >> + vddxo-supply = <&vreg_pmu_xo>;
> >> + vddrf-supply = <&vreg_pmu_rf>;
> >> + vddch0-supply = <&vreg_pmu_ch0>;
> >> + };
> >> +};
> >> +
> >> +&wifi {
> >> + vdd-0.8-cx-mx-supply = <&pm4125_l7>;
> >> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> >> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> >> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> >> + qcom,calibration-variant = "Shikra_EVK";
> >> + firmware-name = "cq2390";
> >> +
> >> + status = "okay";
> >> +};
> >> diff --git a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> >> index 8b03d4eafa6d..a79f44aff968 100644
> >> --- a/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> >> +++ b/arch/arm64/boot/dts/qcom/shikra-evk.dtsi
> >> @@ -8,7 +8,22 @@ &qupv3_0 {
> >> status = "okay";
> >> };
> >>
> >> +&tlmm {
> >> + sw_ctrl_default: sw-ctrl-default-state {
> >> + pins = "gpio88";
> >> + function = "gpio";
> >> + bias-pull-down;
> >> + };
> >> +};
> >> +
> >> &uart0 {
> >> status = "okay";
> >> };
> >>
> >> +&uart8 {
> >> + bluetooth {
> >> + compatible = "qcom,wcn3988-bt";
> >> + max-speed = <3200000>;
> >> + };
> >> +};
> >> +
> >> diff --git a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> >> index 727809430fd1..95bd797d009d 100644
> >> --- a/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> >> +++ b/arch/arm64/boot/dts/qcom/shikra-iqs-evk.dts
> >> @@ -16,11 +16,56 @@ / {
> >> aliases {
> >> mmc0 = &sdhc_1;
> >> serial0 = &uart0;
> >> + serial1 = &uart8;
> >> };
> >>
> >> chosen {
> >> stdout-path = "serial0:115200n8";
> >> };
> >> +
> >> + vreg_wcn_3p3: regulator-wcn-3p3 {
> >> + compatible = "regulator-fixed";
> >> + regulator-name = "wcn_3p3";
> >> + regulator-min-microvolt = <3300000>;
> >> + regulator-max-microvolt = <3300000>;
> >> + regulator-always-on;
> >> + };
> >> +
> >> + wcn3988-pmu {
> >> + compatible = "qcom,wcn3988-pmu";
> >> +
> >> + pinctrl-0 = <&sw_ctrl_default>;
> >> + pinctrl-names = "default";
> >> +
> >> + vddio-supply = <&pm8150_s4>;
> >> + vddxo-supply = <&pm8150_l12>;
> >> + vddrf-supply = <&pm8150_l8>;
> >> + vddch0-supply = <&vreg_wcn_3p3>;
> >> +
> >> + swctrl-gpios = <&tlmm 88 GPIO_ACTIVE_HIGH>;
> >> +
> >> + regulators {
> >> + vreg_pmu_io: ldo0 {
> >> + regulator-name = "vreg_pmu_io";
> >> + };
> >> +
> >> + vreg_pmu_xo: ldo1 {
> >> + regulator-name = "vreg_pmu_xo";
> >> + };
> >> +
> >> + vreg_pmu_rf: ldo2 {
> >> + regulator-name = "vreg_pmu_rf";
> >> + };
> >> +
> >> + vreg_pmu_ch0: ldo3 {
> >> + regulator-name = "vreg_pmu_ch0";
> >> + };
> >> +
> >> + vreg_pmu_ch1: ldo4 {
> >> + regulator-name = "vreg_pmu_ch1";
> >> + };
> >> + };
> >> + };
> >> };
> >>
> >> &remoteproc_cdsp {
> >> @@ -57,3 +102,25 @@ &sdhc_1 {
> >>
> >> status = "okay";
> >> };
> >> +
> >> +&uart8 {
> >> + status = "okay";
> >> +
> >> + bluetooth {
> >> + vddio-supply = <&vreg_pmu_io>;
> >> + vddxo-supply = <&vreg_pmu_xo>;
> >> + vddrf-supply = <&vreg_pmu_rf>;
> >> + vddch0-supply = <&vreg_pmu_ch0>;
> >> + };
> >> +};
> >> +
> >> +&wifi {
> >> + vdd-0.8-cx-mx-supply = <&pm8150_s4>;
> >> + vdd-1.8-xo-supply = <&vreg_pmu_xo>;
> >> + vdd-1.3-rfa-supply = <&vreg_pmu_rf>;
> >> + vdd-3.3-ch0-supply = <&vreg_pmu_ch0>;
> >> + qcom,calibration-variant = "Shikra_EVK";
> >> + firmware-name = "cq2390";
> > Does the firmware differ from the one used on Agatti (QCM2290)?
> Yes, WCN3950 vs WCN3980.
It's not exactly my question, Agatti also supports both (e.g. WCN3988
is integrated to UNO-Q).
Regards,
Loic
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