From: Imran Shaik <imran.shaik@oss.qualcomm.com>
To: Dmitry Baryshkov <dmitry.baryshkov@oss.qualcomm.com>
Cc: Bjorn Andersson <andersson@kernel.org>,
Michael Turquette <mturquette@baylibre.com>,
Stephen Boyd <sboyd@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Konrad Dybcio <konradybcio@kernel.org>,
Loic Poulain <loic.poulain@oss.qualcomm.com>,
Brian Masney <bmasney@redhat.com>,
Ajit Pandey <ajit.pandey@oss.qualcomm.com>,
Taniya Das <taniya.das@oss.qualcomm.com>,
Jagadeesh Kona <jagadeesh.kona@oss.qualcomm.com>,
linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v4 08/13] clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model
Date: Sun, 21 Jun 2026 19:01:33 +0530 [thread overview]
Message-ID: <2fff81bb-1880-4057-b176-dcc9e26a3527@oss.qualcomm.com> (raw)
In-Reply-To: <4zhwpr2n6ihjevwamqzutoyoj4owg3mkutbn3ddstooh566fqy@j2k2or3narkd>
On 06-06-2026 04:59 pm, Dmitry Baryshkov wrote:
> On Thu, Jun 04, 2026 at 10:56:14AM +0530, Imran Shaik wrote:
>> Update the QCM2290 GPUCC driver to use the qcom_cc_probe() model by moving
>> the critical clocks handling and PLL configurations from probe to the
>> driver_data to align with the latest convention. While at it, drop the
>> modelling of gpu_cc_ahb_clk and gpu_cc_cxo_aon_clk clocks and keep them
>
> Why? Also it looks like a separate commit to me.
>
Sure, I will check and split the patches.
>> enabled from probe as per the hardware requirements, and drop pm_clk
>> handling as the required GCC clocks are kept always-on from GCC probe.
>
> Separate commit.
>
Sure.
>>
>> Signed-off-by: Imran Shaik <imran.shaik@oss.qualcomm.com>
>> ---
>> drivers/clk/qcom/gpucc-qcm2290.c | 92 +++++++++-------------------------------
>> 1 file changed, 21 insertions(+), 71 deletions(-)
>>
>> @@ -224,19 +210,6 @@ static struct clk_branch gpu_cc_cx_snoc_dvm_clk = {
>> },
>> };
>>
>> -static struct clk_branch gpu_cc_cxo_aon_clk = {
>> - .halt_reg = 0x1004,
>> - .halt_check = BRANCH_HALT_DELAY,
>> - .clkr = {
>> - .enable_reg = 0x1004,
>> - .enable_mask = BIT(0),
>> - .hw.init = &(struct clk_init_data){
>> - .name = "gpu_cc_cxo_aon_clk",
>> - .ops = &clk_branch2_ops,
>> - },
>> - },
>> -};
>
> This wasn't always-on beforehand. Why is being changed?
>
>> -
>> static struct clk_branch gpu_cc_cxo_clk = {
>> .halt_reg = 0x109c,
>> .halt_check = BRANCH_HALT,
>> @@ -318,12 +291,10 @@ static struct gdsc gpu_gx_gdsc = {
>> };
>>
>> static struct clk_regmap *gpu_cc_qcm2290_clocks[] = {
>> - [GPU_CC_AHB_CLK] = &gpu_cc_ahb_clk.clkr,
>> [GPU_CC_CRC_AHB_CLK] = &gpu_cc_crc_ahb_clk.clkr,
>> [GPU_CC_CX_GFX3D_CLK] = &gpu_cc_cx_gfx3d_clk.clkr,
>> [GPU_CC_CX_GMU_CLK] = &gpu_cc_cx_gmu_clk.clkr,
>> [GPU_CC_CX_SNOC_DVM_CLK] = &gpu_cc_cx_snoc_dvm_clk.clkr,
>> - [GPU_CC_CXO_AON_CLK] = &gpu_cc_cxo_aon_clk.clkr,
>> [GPU_CC_CXO_CLK] = &gpu_cc_cxo_clk.clkr,
>> [GPU_CC_GMU_CLK_SRC] = &gpu_cc_gmu_clk_src.clkr,
>> [GPU_CC_GX_GFX3D_CLK] = &gpu_cc_gx_gfx3d_clk.clkr,
>> @@ -342,6 +313,16 @@ static struct gdsc *gpu_cc_qcm2290_gdscs[] = {
>> [GPU_GX_GDSC] = &gpu_gx_gdsc,
>> };
>>
>> +static struct clk_alpha_pll *gpu_cc_qcm2290_plls[] = {
>> + &gpu_cc_pll0,
>> +};
>> +
>> +static const u32 gpu_cc_qcm2290_critical_cbcrs[] = {
>> + 0x1078, /* GPU_CC_AHB_CLK */
>> + 0x1004, /* GPU_CC_CXO_AON_CLK */
>> + 0x1060, /* GPU_CC_GX_CXO_CLK */
>> +};
>> +
>> static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
>> .reg_bits = 32,
>> .reg_stride = 4,
>> @@ -350,6 +331,12 @@ static const struct regmap_config gpu_cc_qcm2290_regmap_config = {
>> .fast_io = true,
>> };
>>
>> +static const struct qcom_cc_driver_data gpu_cc_qcm2290_driver_data = {
>> + .alpha_plls = gpu_cc_qcm2290_plls,
>> + .num_alpha_plls = ARRAY_SIZE(gpu_cc_qcm2290_plls),
>> + .clk_cbcrs = gpu_cc_qcm2290_critical_cbcrs,
>> + .num_clk_cbcrs = ARRAY_SIZE(gpu_cc_qcm2290_critical_cbcrs),
>> +};
>>
>> static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
>> .config = &gpu_cc_qcm2290_regmap_config,
>> @@ -359,6 +346,7 @@ static const struct qcom_cc_desc gpu_cc_qcm2290_desc = {
>> .num_resets = ARRAY_SIZE(gpu_cc_qcm2290_resets),
>> .gdscs = gpu_cc_qcm2290_gdscs,
>> .num_gdscs = ARRAY_SIZE(gpu_cc_qcm2290_gdscs),
>> + .driver_data = &gpu_cc_qcm2290_driver_data,
>> };
>>
>> static const struct of_device_id gpu_cc_qcm2290_match_table[] = {
>> @@ -369,45 +357,7 @@ MODULE_DEVICE_TABLE(of, gpu_cc_qcm2290_match_table);
>>
>> static int gpu_cc_qcm2290_probe(struct platform_device *pdev)
>> {
>> - struct regmap *regmap;
>> - int ret;
>> -
>> - regmap = qcom_cc_map(pdev, &gpu_cc_qcm2290_desc);
>> - if (IS_ERR(regmap))
>> - return PTR_ERR(regmap);
>> -
>> - ret = devm_pm_runtime_enable(&pdev->dev);
>
> So, it was pm_runtime-enabled beforehand. Now you've silently dropped
> it.
>
My bad, will add use_rpm flag.
Thanks,
Imran
next prev parent reply other threads:[~2026-06-21 13:31 UTC|newest]
Thread overview: 46+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-06-04 5:26 [PATCH v4 00/13] clk: qcom: Add DISPCC and GPUCC support for the Qualcomm Shikra SoC Imran Shaik
2026-06-04 5:26 ` [PATCH v4 01/13] clk: qcom: gcc-qcm2290: Keep the critical clocks always-on from probe Imran Shaik
2026-06-06 11:24 ` Dmitry Baryshkov
2026-06-21 13:28 ` Imran Shaik
2026-06-22 15:12 ` Dmitry Baryshkov
2026-06-23 6:14 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 02/13] dt-bindings: clock: qcom,qcm2290-dispcc: Add DSI1 PHY and sleep clocks Imran Shaik
2026-06-05 10:23 ` Krzysztof Kozlowski
2026-06-21 13:25 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 03/13] dt-bindings: clock: qcom: Add Qualcomm Shikra Display clock controller Imran Shaik
2026-06-05 10:25 ` Krzysztof Kozlowski
2026-06-21 13:26 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 04/13] dt-bindings: clock: qcom: Add Qualcomm Shikra GPU " Imran Shaik
2026-06-05 10:24 ` Krzysztof Kozlowski
2026-06-21 13:27 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 05/13] clk: qcom: dispcc-qcm2290: Move to the latest common qcom_cc_probe() model Imran Shaik
2026-06-06 11:25 ` Dmitry Baryshkov
2026-06-10 13:55 ` Konrad Dybcio
2026-06-04 5:26 ` [PATCH v4 06/13] clk: qcom: dispcc-qcm2290: Switch to DT index based clk lookup Imran Shaik
2026-06-05 10:28 ` Krzysztof Kozlowski
2026-06-21 13:30 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 07/13] clk: qcom: dispcc-qcm2290: Update GDSC *wait_val values and flags Imran Shaik
2026-06-06 11:27 ` Dmitry Baryshkov
2026-06-21 13:30 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 08/13] clk: qcom: gpucc-qcm2290: Move to the latest common qcom_cc_probe() model Imran Shaik
2026-06-06 11:29 ` Dmitry Baryshkov
2026-06-21 13:31 ` Imran Shaik [this message]
2026-06-04 5:26 ` [PATCH v4 09/13] clk: qcom: gpucc-qcm2290: Park RCG's clk source at XO during disable Imran Shaik
2026-06-10 14:00 ` Konrad Dybcio
2026-06-21 13:32 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 10/13] clk: qcom: gpucc-qcm2290: Update GDSC *wait_val values and flags Imran Shaik
2026-06-06 11:31 ` Dmitry Baryshkov
2026-06-21 13:32 ` Imran Shaik
2026-06-04 5:26 ` [PATCH v4 11/13] clk: qcom: Add support for Qualcomm GPU Clock Controller on Shikra Imran Shaik
2026-06-06 11:31 ` Dmitry Baryshkov
2026-06-10 14:00 ` Konrad Dybcio
2026-06-04 5:26 ` [PATCH v4 12/13] arm64: dts: qcom: agatti: Add DSI1 PHY and sleep clocks to DISPCC node Imran Shaik
2026-06-06 11:32 ` Dmitry Baryshkov
2026-06-10 14:02 ` Konrad Dybcio
2026-06-12 7:54 ` Dmitry Baryshkov
2026-06-04 5:26 ` [PATCH v4 13/13] arm64: dts: qcom: shikra: Add support for DISPCC/GPUCC nodes Imran Shaik
2026-06-06 11:33 ` Dmitry Baryshkov
2026-06-25 8:44 ` Konrad Dybcio
2026-06-29 6:43 ` Imran Shaik
2026-06-29 9:51 ` Konrad Dybcio
2026-06-29 11:11 ` Imran Shaik
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