[PATCH] ACPI: CPPC: Reject EPP registers narrower than 8 bits

[PATCH] ACPI: CPPC: Reject EPP registers narrower than 8 bits

[Christian Loehle]

The EPP interfaces use an 8-bit preference, but ACPI permits narrower
fields. With a 4- or 6-bit SystemMemory field, writing 128 succeeds but
stores zero, requesting maximum performance instead.

Reject a present EPP register narrower than eight bits during _CPC probe.
Use the existing error path to release previously acquired resources and
leave the CPU's CPPC descriptor unpublished. Keep absent EPP entries and
registers at least eight bits wide on their existing paths.

Fail the whole probe instead of disabling only EPP. This also makes
amd-pstate's acpi_cpc_valid() check reject the platform before registering
its MSR or shared-memory driver. No affected hardware is known or
expected and the specification is expected to no longer permit these
in the future.

Fixes: 922607a2b462 ("cpufreq: CPPC: Add support for autonomous selection")
Link: https://github.com/tianocore/edk2/issues/10838
Signed-off-by: Christian Loehle <christian.loehle@arm.com>
---
 drivers/acpi/cppc_acpi.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
index 11a9f9eb6b4a..4c3d5778e428 100644
--- a/drivers/acpi/cppc_acpi.c
+++ b/drivers/acpi/cppc_acpi.c
@@ -2094,6 +2094,15 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
 			cpc_apply_platform_quirks(gas_t, i - 2,
 						  platform_quirks);
 
+			/* EPP interfaces require the full 0-255 preference range. */
+			if (i - 2 == ENERGY_PERF && gas_t->bit_width < 8 &&
+			    !IS_NULL_REG(gas_t)) {
+				pr_debug("CPU%d: EPP register width %u is not supported\n",
+					 pr->id, gas_t->bit_width);
+				ret = -EOPNOTSUPP;
+				goto out_free;
+			}
+
 			/*
 			 * The PCC Subspace index is encoded inside
 			 * the CPC table entries. The same PCC index
-- 
2.34.1

Re: [PATCH] ACPI: CPPC: Reject EPP registers narrower than 8 bits

[Mario Limonciello]

On 11/13/26 07:04, Christian Loehle wrote:
> The EPP interfaces use an 8-bit preference, but ACPI permits narrower
> fields. With a 4- or 6-bit SystemMemory field, writing 128 succeeds but
> stores zero, requesting maximum performance instead.
> 
> Reject a present EPP register narrower than eight bits during _CPC probe.
> Use the existing error path to release previously acquired resources and
> leave the CPU's CPPC descriptor unpublished. Keep absent EPP entries and
> registers at least eight bits wide on their existing paths.
> 
> Fail the whole probe instead of disabling only EPP. This also makes
> amd-pstate's acpi_cpc_valid() check reject the platform before registering
> its MSR or shared-memory driver. No affected hardware is known or
> expected and the specification is expected to no longer permit these
> in the future.
> 
> Fixes: 922607a2b462 ("cpufreq: CPPC: Add support for autonomous selection")
> Link: https://github.com/tianocore/edk2/issues/10838
> Signed-off-by: Christian Loehle <christian.loehle@arm.com>

Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>

> ---
>   drivers/acpi/cppc_acpi.c | 9 +++++++++
>   1 file changed, 9 insertions(+)
> 
> diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> index 11a9f9eb6b4a..4c3d5778e428 100644
> --- a/drivers/acpi/cppc_acpi.c
> +++ b/drivers/acpi/cppc_acpi.c
> @@ -2094,6 +2094,15 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
>   			cpc_apply_platform_quirks(gas_t, i - 2,
>   						  platform_quirks);
>   
> +			/* EPP interfaces require the full 0-255 preference range. */
> +			if (i - 2 == ENERGY_PERF && gas_t->bit_width < 8 &&
> +			    !IS_NULL_REG(gas_t)) {
> +				pr_debug("CPU%d: EPP register width %u is not supported\n",
> +					 pr->id, gas_t->bit_width);
> +				ret = -EOPNOTSUPP;
> +				goto out_free;
> +			}
> +
>   			/*
>   			 * The PCC Subspace index is encoded inside
>   			 * the CPC table entries. The same PCC index

Re: [PATCH] ACPI: CPPC: Reject EPP registers narrower than 8 bits

[Rafael J. Wysocki (Intel)]

On Fri, Nov 13, 2026 at 2:52 PM Mario Limonciello <superm1@kernel.org> wrote:
>
> On 11/13/26 07:04, Christian Loehle wrote:
> > The EPP interfaces use an 8-bit preference, but ACPI permits narrower
> > fields. With a 4- or 6-bit SystemMemory field, writing 128 succeeds but
> > stores zero, requesting maximum performance instead.
> >
> > Reject a present EPP register narrower than eight bits during _CPC probe.
> > Use the existing error path to release previously acquired resources and
> > leave the CPU's CPPC descriptor unpublished. Keep absent EPP entries and
> > registers at least eight bits wide on their existing paths.
> >
> > Fail the whole probe instead of disabling only EPP. This also makes
> > amd-pstate's acpi_cpc_valid() check reject the platform before registering
> > its MSR or shared-memory driver. No affected hardware is known or
> > expected and the specification is expected to no longer permit these
> > in the future.
> >
> > Fixes: 922607a2b462 ("cpufreq: CPPC: Add support for autonomous selection")
> > Link: https://github.com/tianocore/edk2/issues/10838
> > Signed-off-by: Christian Loehle <christian.loehle@arm.com>
>
> Reviewed-by: Mario Limonciello (AMD) <superm1@kernel.org>

Applied as 7.4-rc material, thanks!

> > ---
> >   drivers/acpi/cppc_acpi.c | 9 +++++++++
> >   1 file changed, 9 insertions(+)
> >
> > diff --git a/drivers/acpi/cppc_acpi.c b/drivers/acpi/cppc_acpi.c
> > index 11a9f9eb6b4a..4c3d5778e428 100644
> > --- a/drivers/acpi/cppc_acpi.c
> > +++ b/drivers/acpi/cppc_acpi.c
> > @@ -2094,6 +2094,15 @@ int acpi_cppc_processor_probe(struct acpi_processor *pr)
> >                       cpc_apply_platform_quirks(gas_t, i - 2,
> >                                                 platform_quirks);
> >
> > +                     /* EPP interfaces require the full 0-255 preference range. */
> > +                     if (i - 2 == ENERGY_PERF && gas_t->bit_width < 8 &&
> > +                         !IS_NULL_REG(gas_t)) {
> > +                             pr_debug("CPU%d: EPP register width %u is not supported\n",
> > +                                      pr->id, gas_t->bit_width);
> > +                             ret = -EOPNOTSUPP;
> > +                             goto out_free;
> > +                     }
> > +
> >                       /*
> >                        * The PCC Subspace index is encoded inside
> >                        * the CPC table entries. The same PCC index
>