Re: [PATCH 4/4] arm64: dts: qcom: msm8939: Add camss and cci

[Bryan O'Donoghue <bryan.odonoghue@linaro.org>]

On 20/05/2025 19:39, Vincent Knecht via B4 Relay wrote:
> From: Vincent Knecht <vincent.knecht@mailoo.org>
> 
> Add the camera subsystem and CCI used to interface with cameras on the
> Snapdragon 615.
> 
> Signed-off-by: Vincent Knecht <vincent.knecht@mailoo.org>
> ---
>   arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi |   4 +
>   arch/arm64/boot/dts/qcom/msm8939.dtsi        | 152 +++++++++++++++++++++++++++
>   2 files changed, 156 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
> index adb96cd8d643e5fde1ac95c0fc3c9c3c3efb07e8..659d127b1bc3570d137ca986e4eacf600c183e5e 100644
> --- a/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8939-pm8916.dtsi
> @@ -11,6 +11,10 @@
>   #include "msm8939.dtsi"
>   #include "pm8916.dtsi"
>   
> +&camss {
> +	vdda-supply = <&pm8916_l2>;
> +};
> +
>   &mdss_dsi0 {
>   	vdda-supply = <&pm8916_l2>;
>   	vddio-supply = <&pm8916_l6>;
> diff --git a/arch/arm64/boot/dts/qcom/msm8939.dtsi b/arch/arm64/boot/dts/qcom/msm8939.dtsi
> index 68b92fdb996c26e7a1aadedf0f52e1afca85c4ab..af4d865b6858f13559838031910bee37b58aca3c 100644
> --- a/arch/arm64/boot/dts/qcom/msm8939.dtsi
> +++ b/arch/arm64/boot/dts/qcom/msm8939.dtsi
> @@ -1434,6 +1434,151 @@ mdss_dsi1_phy: phy@1aa0300 {
>   			};
>   		};
>   
> +		camss: camss@1b0ac00 {

isp@

> +			compatible = "qcom,msm8939-camss";
> +			reg = <0x01b0ac00 0x200>,
<0x01b0ac00 0x0 0x200 0x0>

> +			      <0x01b00030 0x4>,
> +			      <0x01b0b000 0x200>,
> +			      <0x01b00038 0x4>,
> +			      <0x01b08000 0x100>,
> +			      <0x01b08400 0x100>,
> +			      <0x01b08800 0x100>,
> +			      <0x01b0a000 0x500>,
> +			      <0x01b00020 0x10>,
> +			      <0x01b10000 0x1000>,
> +			      <0x01b40000 0x200>;
> +			reg-names = "csiphy0",
> +				    "csiphy0_clk_mux",
> +				    "csiphy1",
> +				    "csiphy1_clk_mux",
> +				    "csid0",
> +				    "csid1",
> +				    "csid2",
> +				    "ispif",
> +				    "csi_clk_mux",
> +				    "vfe0",
> +				    "vfe0_vbif";
> +
> +			interrupts = <GIC_SPI 78 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 79 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 51 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 52 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 153 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 55 IRQ_TYPE_EDGE_RISING>,
> +				     <GIC_SPI 57 IRQ_TYPE_EDGE_RISING>;
> +			interrupt-names = "csiphy0",
> +					  "csiphy1",
> +					  "csid0",
> +					  "csid1",
> +					  "csid2",
> +					  "ispif",
> +					  "vfe0";
> +
> +			power-domains = <&gcc VFE_GDSC>;
> +
> +			clocks = <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_CSI0PHYTIMER_CLK>,
> +				 <&gcc GCC_CAMSS_CSI1PHYTIMER_CLK>,
> +				 <&gcc GCC_CAMSS_CSI0_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_CSI0_CLK>,
> +				 <&gcc GCC_CAMSS_CSI0PHY_CLK>,
> +				 <&gcc GCC_CAMSS_CSI0PIX_CLK>,
> +				 <&gcc GCC_CAMSS_CSI0RDI_CLK>,
> +				 <&gcc GCC_CAMSS_CSI1_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_CSI1_CLK>,
> +				 <&gcc GCC_CAMSS_CSI1PHY_CLK>,
> +				 <&gcc GCC_CAMSS_CSI1PIX_CLK>,
> +				 <&gcc GCC_CAMSS_CSI1RDI_CLK>,
> +				 <&gcc GCC_CAMSS_CSI2_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_CSI2_CLK>,
> +				 <&gcc GCC_CAMSS_CSI2PHY_CLK>,
> +				 <&gcc GCC_CAMSS_CSI2PIX_CLK>,
> +				 <&gcc GCC_CAMSS_CSI2RDI_CLK>,
> +				 <&gcc GCC_CAMSS_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_VFE0_CLK>,
> +				 <&gcc GCC_CAMSS_CSI_VFE0_CLK>,
> +				 <&gcc GCC_CAMSS_VFE_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_VFE_AXI_CLK>;
> +			clock-names = "top_ahb",
> +				      "ispif_ahb",
> +				      "csiphy0_timer",
> +				      "csiphy1_timer",
> +				      "csi0_ahb",
> +				      "csi0",
> +				      "csi0_phy",
> +				      "csi0_pix",
> +				      "csi0_rdi",
> +				      "csi1_ahb",
> +				      "csi1",
> +				      "csi1_phy",
> +				      "csi1_pix",
> +				      "csi1_rdi",
> +				      "csi2_ahb",
> +				      "csi2",
> +				      "csi2_phy",
> +				      "csi2_pix",
> +				      "csi2_rdi",
> +				      "ahb",
> +				      "vfe0",
> +				      "csi_vfe0",
> +				      "vfe_ahb",
> +				      "vfe_axi";
> +
> +			iommus = <&apps_iommu 3>;
> +
> +			status = "disabled";
> +
> +			ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +
> +				port@0 {
> +					reg = <0>;
> +				};
> +
> +				port@1 {
> +					reg = <1>;
> +				};
> +			};
> +		};
> +
> +		cci: cci@1b0c000 {
> +			compatible = "qcom,msm8916-cci", "qcom,msm8226-cci";
> +			#address-cells = <1>;
> +			#size-cells = <0>;
> +			reg = <0x01b0c000 0x1000>;
> +			interrupts = <GIC_SPI 50 IRQ_TYPE_EDGE_RISING>;
> +
> +			clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_TOP_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_CCI_AHB_CLK>,
> +				 <&gcc GCC_CAMSS_CCI_CLK>,
> +				 <&gcc GCC_CAMSS_AHB_CLK>;
> +			clock-names = "ispif_ahb",
> +				      "camss_top_ahb",
> +				      "cci_ahb",
> +				      "cci",
> +				      "camss_ahb";
> +
> +			assigned-clocks = <&gcc GCC_CAMSS_ISPIF_AHB_CLK>,
> +					  <&gcc GCC_CAMSS_CCI_CLK>;
> +			assigned-clock-rates = <80000000>,
> +					       <19200000>;
> +
> +			pinctrl-names = "default";
> +			pinctrl-0 = <&cci0_default>;
> +
> +			status = "disabled";
> +
> +			cci_i2c0: i2c-bus@0 {
> +				reg = <0>;
> +				clock-frequency = <400000>;
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +			};
> +		};
> +
>   		gpu: gpu@1c00000 {
>   			compatible = "qcom,adreno-405.0", "qcom,adreno";
>   			reg = <0x01c00000 0x10000>;
> @@ -1498,6 +1643,13 @@ apps_iommu: iommu@1ef0000 {
>   			#iommu-cells = <1>;
>   			qcom,iommu-secure-id = <17>;
>   
> +			/* vfe */
> +			iommu-ctx@3000 {
> +				compatible = "qcom,msm-iommu-v1-sec";
> +				reg = <0x3000 0x1000>;
> +				interrupts = <GIC_SPI 70 IRQ_TYPE_LEVEL_HIGH>;
> +			};
> +
>   			/* mdp_0: */
>   			iommu-ctx@4000 {
>   				compatible = "qcom,msm-iommu-v1-ns";
>