From: Dave Hansen <dave.hansen@intel.com>
To: Baolu Lu <baolu.lu@linux.intel.com>,
Joerg Roedel <joro@8bytes.org>, Will Deacon <will@kernel.org>,
Robin Murphy <robin.murphy@arm.com>,
Kevin Tian <kevin.tian@intel.com>,
Jason Gunthorpe <jgg@nvidia.com>, Jann Horn <jannh@google.com>,
Vasant Hegde <vasant.hegde@amd.com>,
Alistair Popple <apopple@nvidia.com>,
Peter Zijlstra <peterz@infradead.org>,
Uladzislau Rezki <urezki@gmail.com>,
Jean-Philippe Brucker <jean-philippe@linaro.org>,
Andy Lutomirski <luto@kernel.org>,
"Tested-by : Yi Lai" <yi1.lai@intel.com>
Cc: iommu@lists.linux.dev, security@kernel.org,
linux-kernel@vger.kernel.org, stable@vger.kernel.org
Subject: Re: [PATCH v2 1/1] iommu/sva: Invalidate KVA range on kernel TLB flush
Date: Thu, 10 Jul 2025 05:53:16 -0700 [thread overview]
Message-ID: <326c60aa-37f3-458d-a534-6e0106cc244b@intel.com> (raw)
In-Reply-To: <228cd2c9-b781-4505-8b54-42dab03f3650@linux.intel.com>
On 7/9/25 19:14, Baolu Lu wrote:
>> If the problem is truly limited to freeing page tables, it needs to be
>> commented appropriately.
>
> Yeah, good comments. It should not be limited to freeing page tables;
> freeing page tables is just a real case that we can see in the vmalloc/
> vfree paths. Theoretically, whenever a kernel page table update is done
> and the CPU TLB needs to be flushed, the secondary TLB (i.e., the caches
> on the IOMMU) should be flushed accordingly. It's assumed that this
> happens in flush_tlb_kernel_range().
Could you elaborate on this a bit further?
I thought that the IOMMU was only ever doing "user" permission walks and
never "supervisor". That's why we had the whole discussion about whether
the IOMMU would stop if it saw an upper-level entry with _PAGE_USER clear.
The reason this matters is that leaf kernel page table entries always
have _PAGE_USER clear. That means an IOMMU doing "user" permission walks
should never be able to do anything with them. Even if an IOTLB entry
was created* for a _PAGE_USER=0 PTE, the "user" permission walk will
stop when it finds that entry.
It doesn't matter if the entry is stale or not. The "user" permission
IOMMU walk can't do anything with the supervisor mapping.
Why does this matter? We flush the CPU TLB in a bunch of different ways,
_especially_ when it's being done for kernel mappings. For example,
__flush_tlb_all() is a non-ranged kernel flush which has a completely
parallel implementation with flush_tlb_kernel_range(). Call sites that
use _it_ are unaffected by the patch here.
Basically, if we're only worried about vmalloc/vfree freeing page
tables, then this patch is OK. If the problem is bigger than that, then
we need a more comprehensive patch.
* I'm not sure if the IOMMU will even create an IOTLB entry for
a supervisor-permission mapping while doing a user-permission walk.
next prev parent reply other threads:[~2025-07-10 12:49 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-07-09 6:28 Lu Baolu
2025-07-09 15:29 ` Dave Hansen
2025-07-10 2:14 ` Baolu Lu
2025-07-10 2:55 ` Tian, Kevin
2025-07-10 12:53 ` Dave Hansen [this message]
2025-07-10 13:22 ` Jason Gunthorpe
2025-07-10 15:26 ` Dave Hansen
2025-07-11 2:46 ` Tian, Kevin
2025-07-11 2:54 ` Tian, Kevin
2025-07-11 8:17 ` Yu Zhang
2025-07-24 3:01 ` Baolu Lu
2025-07-28 17:36 ` Yu Zhang
2025-07-29 2:08 ` Baolu Lu
2025-07-24 3:06 ` Baolu Lu
2025-07-11 2:49 ` Tian, Kevin
2025-07-10 3:02 ` Tian, Kevin
2025-07-10 8:11 ` Yu Zhang
2025-07-10 8:15 ` Tian, Kevin
2025-07-10 9:37 ` Yu Zhang
2025-07-10 13:54 ` Peter Zijlstra
2025-07-10 15:53 ` Peter Zijlstra
2025-07-11 3:09 ` Baolu Lu
2025-07-11 8:27 ` Peter Zijlstra
2025-07-16 11:57 ` David Laight
2025-07-17 1:47 ` Baolu Lu
2025-07-11 3:00 ` Baolu Lu
2025-07-11 4:01 ` Tian, Kevin
2025-07-11 8:32 ` Peter Zijlstra
2025-07-11 11:58 ` Jason Gunthorpe
2025-07-15 5:55 ` Baolu Lu
2025-07-15 12:25 ` Jason Gunthorpe
2025-07-16 6:34 ` Baolu Lu
2025-07-16 12:08 ` Jason Gunthorpe
2025-07-17 1:43 ` Baolu Lu
2025-07-17 11:50 ` Vasant Hegde
2025-07-11 11:54 ` Jason Gunthorpe
2025-07-16 10:54 ` Yi Liu
2025-07-17 1:51 ` Baolu Lu
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