Re: [PATCH 4/4] phy: qcom: qmp-pcie: Add support for Glymur PCIe Gen5x4 PHY

["Wenbin Yao (Consultant)" <wenbin.yao@oss.qualcomm.com>]

On 8/20/2025 2:43 AM, Dmitry Baryshkov wrote:
> On Tue, Aug 19, 2025 at 02:52:08AM -0700, Wenbin Yao wrote:
>> From: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>>
>> Add support for Gen5 x4 PCIe QMP PHY found on Glymur platform.
>>
>> Signed-off-by: Prudhvi Yarlagadda <quic_pyarlaga@quicinc.com>
>> Signed-off-by: Wenbin Yao <wenbin.yao@oss.qualcomm.com>
>> ---
>>   drivers/phy/qualcomm/phy-qcom-qmp-pcie.c | 29 +++++++++++++++++++++++++++++
>>   1 file changed, 29 insertions(+)
>>
>> diff --git a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> index 95830dcfdec9b1f68fd55d1cc3c102985cfafcc1..e422cf6932d261074ed3419ed8806e9ed212c26c 100644
>> --- a/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> +++ b/drivers/phy/qualcomm/phy-qcom-qmp-pcie.c
>> @@ -93,6 +93,12 @@ static const unsigned int pciephy_v6_regs_layout[QPHY_LAYOUT_SIZE] = {
>>   	[QPHY_PCS_POWER_DOWN_CONTROL]	= QPHY_V6_PCS_POWER_DOWN_CONTROL,
>>   };
>>   
>> +static const unsigned int pciephy_v8_50_regs_layout[QPHY_LAYOUT_SIZE] = {
>> +	[QPHY_START_CTRL]		= QPHY_V8_50_PCS_START_CONTROL,
>> +	[QPHY_PCS_STATUS]		= QPHY_V8_50_PCS_STATUS1,
>> +	[QPHY_PCS_POWER_DOWN_CONTROL]   = QPHY_V8_50_PCS_POWER_DOWN_CONTROL,
>> +};
>> +
>>   static const struct qmp_phy_init_tbl msm8998_pcie_serdes_tbl[] = {
>>   	QMP_PHY_INIT_CFG(QSERDES_V3_COM_BIAS_EN_CLKBUFLR_EN, 0x14),
>>   	QMP_PHY_INIT_CFG(QSERDES_V3_COM_CLK_SELECT, 0x30),
>> @@ -3229,6 +3235,10 @@ static const struct qmp_pcie_offsets qmp_pcie_offsets_v6_30 = {
>>   	.ln_shrd	= 0x8000,
>>   };
>>   
>> +static const struct qmp_pcie_offsets qmp_pcie_offsets_v8_50 = {
>> +	.pcs        = 0x9000,
> Even if the driver uses only PCS regs for 8.50 currently, I'd suggest
> describing the whole picture here. Otherwise it might backfire later, if
> we add offsets for other blocks later and they won't match the ones used
> for Glymur.

OK，will add them.

>
>> +};
>> +
>>   static const struct qmp_phy_cfg ipq8074_pciephy_cfg = {
>>   	.lanes			= 1,
>>   
>> @@ -4258,6 +4268,22 @@ static const struct qmp_phy_cfg qmp_v6_gen4x4_pciephy_cfg = {
>>   	.phy_status             = PHYSTATUS_4_20,
>>   };
>>   
>> +static const struct qmp_phy_cfg glymur_qmp_gen5x4_pciephy_cfg = {
>> +	.lanes = 4,
>> +
>> +	.offsets        = &qmp_pcie_offsets_v8_50,
>> +
>> +	.reset_list     = sdm845_pciephy_reset_l,
>> +	.num_resets     = ARRAY_SIZE(sdm845_pciephy_reset_l),
>> +	.vreg_list      = sm8550_qmp_phy_vreg_l,
>> +	.num_vregs      = ARRAY_SIZE(sm8550_qmp_phy_vreg_l),
>> +
>> +	.regs           = pciephy_v8_50_regs_layout,
>> +
>> +	.pwrdn_ctrl     = SW_PWRDN | REFCLK_DRV_DSBL,
>> +	.phy_status     = PHYSTATUS_4_20,
>> +};
>> +
>>   static void qmp_pcie_init_port_b(struct qmp_pcie *qmp, const struct qmp_phy_cfg_tbls *tbls)
>>   {
>>   	const struct qmp_phy_cfg *cfg = qmp->cfg;
>> @@ -5114,6 +5140,9 @@ static const struct of_device_id qmp_pcie_of_match_table[] = {
>>   	}, {
>>   		.compatible = "qcom,x1p42100-qmp-gen4x4-pcie-phy",
>>   		.data = &qmp_v6_gen4x4_pciephy_cfg,
>> +	}, {
>> +		.compatible = "qcom,glymur-qmp-gen5x4-pcie-phy",
>> +		.data = &glymur_qmp_gen5x4_pciephy_cfg,
>>   	},
>>   	{ },
>>   };
>>
>> -- 
>> 2.34.1
>>
-- 
With best wishes
Wenbin