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From: Meghana Malladi <m-malladi@ti.com>
To: Marc Zyngier <maz@kernel.org>
Cc: MD Danish Anwar <danishanwar@ti.com>,
	Grzegorz Jaszczyk <grzegorz.jaszczyk@linaro.org>,
	Suman Anna <s-anna@ti.com>, David Lechner <david@lechnology.com>,
	Roger Quadros <rogerq@kernel.org>, "Andrew F. Davis" <afd@ti.com>,
	Thomas Gleixner <tglx@linutronix.de>,
	<linux-kernel@vger.kernel.org>, <srk@ti.com>,
	<r-gunasekaran@ti.com>, <vigneshr@ti.com>
Subject: Re: [PATCH 3/3] irqchip/irq-pruss-intc: Fix processing of IEP interrupts
Date: Wed, 18 Feb 2026 16:56:16 +0530	[thread overview]
Message-ID: <3486f2bb-439d-4f7e-aad5-8345fba0283b@ti.com> (raw)
In-Reply-To: <86zf569utc.wl-maz@kernel.org>

Hi Marc,

On 2/18/26 16:34, Marc Zyngier wrote:
> On Wed, 18 Feb 2026 07:08:45 +0000,
> Meghana Malladi <m-malladi@ti.com> wrote:
>>
>> Hi Marc,
>>
>> On 9/19/23 13:02, Marc Zyngier wrote:
>>> On Tue, 19 Sep 2023 07:19:00 +0100,
>>> MD Danish Anwar <danishanwar@ti.com> wrote:
>>>>
>>>> From: Suman Anna <s-anna@ti.com>
>>>>
>>>> It was discovered that IEP capture/compare IRQs (event #7 on all SoCs
>>>> and event #56 on K3 SoCs) are always triggered twice when PPS is
>>>> generated and CMP hit event detected by IEP.
>>>>
>>>> An example of the problem is:
>>>>     pruss_intc_irq_handler
>>>>      generic_handle_irq
>>>>       handle_level_irq
>>>>         mask_ack_irq -> IRQ 7 masked and asked in INTC,
>>>>                         but it's not yet cleared on HW level
>>>>         handle_irq_event()
>>>>           <threaded on RT>
>>>>              icss_iep_cap_cmp_handler() -> IRQ 7 is actually processed in HW
>>>>           irq_finalize_oneshot()
>>>>            unmask_irq()
>>>>              pruss_intc_irq_unmask() -> IRQ 7 status is still observed as set
>>>>
>>>> The solution is to actually ack these IRQs from pruss_intc_irq_unmask()
>>>> after the IRQ source is cleared in HW.
>>>
>>> What you don't explain is whether the interrupt is level or edge
>>> triggered? If it is level, then the "quirk" is that the interrupt
>>> controller is slow to recognise that the level has changed. If it is
>>> edge, this is a guaranteed recipe to lose interrupts.
>>>
>>
>> These are level IRQs, but INTC has latency detecting the source
>> deassertion, causing the double delivery (The hardware keeps the event
>> asserted until cleared in IEP) - I will add more details about this
>> fix in the commit message for v2.
> 
> I'm sorry, but this comes almost 3 years late, and I've long forgotten
> about all of this. I can only conclude that if you (TI, not you
> personally) waited for this long to address my comments, then this is
> probably not something we really need to care about.
> 

Thanks for your reply. I understand the concern about the delay and the 
difficulty in revisiting something after such a long gap.

This work resurfaced now because we are in the process of migrating to 
the 6.18 LTS kernel, and while validating the migration we encountered 
these issues again. For our platforms, these fixes are required to get 
PPS and timestamp functionality working correctly, and for ensuring 
long-term stability.

I realize this comes a long time after the original discussion, but I 
would like to get the patches into the proper shape and aligned with 
your feedback. Thanks again for your time and guidance.

Best,
Meghana


> Thanks,
> 
> 	M.
> 


  reply	other threads:[~2026-02-18 11:26 UTC|newest]

Thread overview: 9+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-09-19  6:18 [PATCH 0/3] Bug Fixes for PRUSS irqchip driver MD Danish Anwar
2023-09-19  6:18 ` [PATCH 1/3] irqchip/irq-pruss-intc: Fix enabling of intc events MD Danish Anwar
2023-09-19  6:18 ` [PATCH 2/3] irqchip/irq-pruss-intc: Fix listed IRQ type in /proc/interrupts MD Danish Anwar
2023-09-19  6:19 ` [PATCH 3/3] irqchip/irq-pruss-intc: Fix processing of IEP interrupts MD Danish Anwar
2023-09-19  7:32   ` Marc Zyngier
2026-02-18  7:08     ` Meghana Malladi
2026-02-18 11:04       ` Marc Zyngier
2026-02-18 11:26         ` Meghana Malladi [this message]
2026-02-22 20:59           ` Thomas Gleixner

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