From: Taniya Das <taniya.das@oss.qualcomm.com>
To: patches@brar.si, Bjorn Andersson <andersson@kernel.org>,
Abel Vesa <abelvesa@kernel.org>, Stephen Boyd <sboyd@kernel.org>,
Brian Masney <bmasney+clk@redhat.com>,
Jerome Brunet <jbrunet+clk@baylibre.com>,
Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Conor Dooley <conor+dt@kernel.org>,
Imran Shaik <quic_imrashai@quicinc.com>
Cc: linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org,
devicetree@vger.kernel.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 2/2] clk: qcom: Add SM7250 graphics clock controller driver
Date: Tue, 27 Oct 2026 11:59:19 +0530 [thread overview]
Message-ID: <34a17861-771c-485f-ba41-6bb2d539ab3f@oss.qualcomm.com> (raw)
In-Reply-To: <20261027-gpucc-sm7250-v2-2-773056e4043e@brar.si>
On 10/27/2026 10:05 AM, Ishu Brar via B4 Relay wrote:
> static const struct qcom_cc_desc gpu_cc_sm7250_desc = {
> + .config = &gpu_cc_sm7250_regmap_config,
> + .clks = gpu_cc_sm7250_clocks,
> + .num_clks = ARRAY_SIZE(gpu_cc_sm7250_clocks),
> + .resets = gpu_cc_sm7250_resets,
> + .num_resets = ARRAY_SIZE(gpu_cc_sm7250_resets),
> + .gdscs = gpu_cc_sm7250_gdscs,
> + .num_gdscs = ARRAY_SIZE(gpu_cc_sm7250_gdscs),
> + .driver_data = &gpu_cc_sm7250_driver_data,
use_rpm = true,
--
Thanks,
Taniya Das
next prev parent reply other threads:[~2026-10-27 6:29 UTC|newest]
Thread overview: 6+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 4:35 [PATCH v2 0/2] clk: qcom: Add SM7250 graphics clock controller Ishu Brar via B4 Relay
2026-10-27 4:35 ` [PATCH v2 1/2] dt-bindings: clock: " Ishu Brar via B4 Relay
2026-10-27 4:35 ` [PATCH v2 2/2] clk: qcom: Add SM7250 graphics clock controller driver Ishu Brar via B4 Relay
2026-10-27 6:29 ` Taniya Das [this message]
2026-10-27 11:32 ` Abel Vesa
2026-10-27 12:14 ` Konrad Dybcio
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