Re: [PATCH v2 2/2] clk: qcom: Add SM7250 graphics clock controller driver

[Konrad Dybcio <konrad.dybcio@oss.qualcomm.com>]

On 10/27/26 5:35 AM, Ishu Brar via B4 Relay wrote:
> From: Ishu Brar <patches@brar.si>
> 
> Add a driver for the graphics clock controller of the Qualcomm SM7250
> SoC (Snapdragon 765/765G/768G). It provides the GMU clock and its PLL,
> the GPU CX and GX power domains, and the GPU SMMU vote clock. The layout
> follows the SM8250 driver, since both use a Lucid PLL and the same GMU
> clock setup; the PLL settings, frequency table, register offsets and
> GDSC data come from the downstream driver of the platform.

[...]

> +#define CX_GMU_CBCR_SLEEP_MASK		0xf
> +#define CX_GMU_CBCR_SLEEP_SHIFT		4
> +#define CX_GMU_CBCR_WAKE_MASK		0xf
> +#define CX_GMU_CBCR_WAKE_SHIFT		8

#define CX_GMU_CBCR_SLEEP_MASK		GENMASK(7, 4)
#define CX_GMU_CBCR_WAKE_MASK		GENMASK(11, 8)

[...]

> +static void gpu_cc_sm7250_regs_configure(struct device *dev, struct regmap *regmap)
> +{
> +	unsigned int value, mask;
> +
> +	/*
> +	 * Configure gpu_cc_cx_gmu_clk with recommended
> +	 * wakeup/sleep settings
> +	 */
> +	mask = CX_GMU_CBCR_WAKE_MASK << CX_GMU_CBCR_WAKE_SHIFT;
> +	mask |= CX_GMU_CBCR_SLEEP_MASK << CX_GMU_CBCR_SLEEP_SHIFT;
> +	value = 0xf << CX_GMU_CBCR_WAKE_SHIFT | 0xf << CX_GMU_CBCR_SLEEP_SHIFT;
> +	regmap_update_bits(regmap, 0x1098, mask, value);

and then here:

mask = CX_GMU_CBCR_WAKE_MASK | CX_GMU_CBCR_SLEEP_MASK;
value = FIELD_PREP(CX_GMU_CBCR_WAKE_MASK, 0xf) |
	FIELD_PREP(CX_GMU_CBCR_SLEEP_MASK, 0xf);
regmap_update_bits(regmap, 0x1098, mask, value);


you'll also want .use_rpm in the desc struct

Konrad