From: <Conor.Dooley@microchip.com>
To: <prabhakar.csengg@gmail.com>, <geert+renesas@glider.be>,
<robh+dt@kernel.org>, <krzysztof.kozlowski+dt@linaro.org>,
<paul.walmsley@sifive.com>, <palmer@dabbelt.com>,
<aou@eecs.berkeley.edu>
Cc: <heiko@sntech.de>, <atishp@rivosinc.com>,
<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
<linux-renesas-soc@vger.kernel.org>,
<linux-kernel@vger.kernel.org>, <biju.das.jz@bp.renesas.com>,
<prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes
Date: Thu, 15 Sep 2022 21:36:02 +0000 [thread overview]
Message-ID: <3693a3a1-5a2a-4cc5-fb55-f6ad9a4b3f72@microchip.com> (raw)
In-Reply-To: <20220915181558.354737-8-prabhakar.mahadev-lad.rj@bp.renesas.com>
On 15/09/2022 19:15, Prabhakar wrote:
> riscv: boot: dts: r9a07g043: Add placeholder nodes
nit: s/boot//
> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>
> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>
> Add empty placeholder nodes to RZ/Five (R9A07G043) SoC DTSI.
Can you explain why do you need placeholder nodes for this and
cannot just directly include the other dtsis?
>
> This is in preparation to reuse the RZ/G2UL SMARC SoM and carrier
> board DTS/I.
>
> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
> ---
> v1->v3
> * New patch
> ---
> arch/riscv/boot/dts/renesas/r9a07g043.dtsi | 177 +++++++++++++++++++++
> 1 file changed, 177 insertions(+)
>
> diff --git a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> index fb6733f3cc2b..6d9db759a847 100644
> --- a/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/riscv/boot/dts/renesas/r9a07g043.dtsi
> @@ -13,6 +13,14 @@ / {
> #address-cells = <2>;
> #size-cells = <2>;
>
> + audio_clk1: audio1-clk {
> + /* placeholder */
> + };
> +
> + audio_clk2: audio2-clk {
> + /* placeholder */
> + };
> +
> cpus {
> #address-cells = <1>;
> #size-cells = <0>;
> @@ -54,6 +62,23 @@ soc: soc {
> #size-cells = <2>;
> ranges;
>
> + ssi1: ssi@1004a000 {
> + reg = <0 0x1004a000 0 0x400>;
> + #sound-dai-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + spi1: spi@1004b000 {
> + reg = <0 0x1004b000 0 0x400>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> scif0: serial@1004b800 {
> compatible = "renesas,scif-r9a07g043",
> "renesas,scif-r9a07g044";
> @@ -73,6 +98,48 @@ scif0: serial@1004b800 {
> status = "disabled";
> };
>
> + canfd: can@10050000 {
> + reg = <0 0x10050000 0 0x8000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + i2c0: i2c@10058000 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x10058000 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + i2c1: i2c@10058400 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + reg = <0 0x10058400 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + adc: adc@10059000 {
> + reg = <0 0x10059000 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + sbc: spi@10060000 {
> + reg = <0 0x10060000 0 0x10000>,
> + <0 0x20000000 0 0x10000000>,
> + <0 0x10070000 0 0x10000>;
> + reg-names = "regs", "dirmap", "wbuf";
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> cpg: clock-controller@11010000 {
> compatible = "renesas,r9a07g043-cpg";
> reg = <0 0x11010000 0 0x10000>;
> @@ -104,6 +171,95 @@ pinctrl: pinctrl@11030000 {
> <&cpg R9A07G043_GPIO_SPARE_RESETN>;
> };
>
> + sdhi0: mmc@11c00000 {
> + reg = <0x0 0x11c00000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + sdhi1: mmc@11c10000 {
> + reg = <0x0 0x11c10000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + eth0: ethernet@11c20000 {
> + reg = <0 0x11c20000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + eth1: ethernet@11c30000 {
> + reg = <0 0x11c30000 0 0x10000>;
> + #address-cells = <1>;
> + #size-cells = <0>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + phyrst: usbphy-ctrl@11c40000 {
> + reg = <0 0x11c40000 0 0x10000>;
> + #reset-cells = <1>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ohci0: usb@11c50000 {
> + reg = <0 0x11c50000 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ohci1: usb@11c70000 {
> + reg = <0 0x11c70000 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ehci0: usb@11c50100 {
> + reg = <0 0x11c50100 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ehci1: usb@11c70100 {
> + reg = <0 0x11c70100 0 0x100>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + usb2_phy0: usb-phy@11c50200 {
> + reg = <0 0x11c50200 0 0x700>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + usb2_phy1: usb-phy@11c70200 {
> + reg = <0 0x11c70200 0 0x700>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + hsusb: usb@11c60000 {
> + reg = <0 0x11c60000 0 0x10000>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> plic: interrupt-controller@12c00000 {
> compatible = "renesas,r9a07g043-plic", "andestech,nceplic100";
> #interrupt-cells = <2>;
> @@ -116,5 +272,26 @@ plic: interrupt-controller@12c00000 {
> resets = <&cpg R9A07G043_NCEPLIC_ARESETN>;
> interrupts-extended = <&cpu0_intc 11 &cpu0_intc 9>;
> };
> +
> + wdt0: watchdog@12800800 {
> + reg = <0 0x12800800 0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ostm1: timer@12801400 {
> + reg = <0x0 0x12801400 0x0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> +
> + ostm2: timer@12801800 {
> + reg = <0x0 0x12801800 0x0 0x400>;
> + status = "disabled";
> +
> + /* placeholder */
> + };
> };
> };
> --
> 2.25.1
>
next prev parent reply other threads:[~2022-09-15 21:36 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-09-15 18:15 [PATCH v3 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-15 21:13 ` Conor.Dooley
2022-09-15 21:56 ` Lad, Prabhakar
2022-09-20 12:00 ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-15 20:53 ` Heiko Stuebner
2022-09-15 18:15 ` [PATCH v3 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-15 18:15 ` [PATCH v3 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Prabhakar
2022-09-15 20:58 ` Conor.Dooley
2022-09-15 22:18 ` Lad, Prabhakar
2022-09-15 22:25 ` Conor.Dooley
2022-09-15 18:15 ` [PATCH v3 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-15 21:36 ` Conor.Dooley [this message]
2022-09-15 22:26 ` Lad, Prabhakar
2022-09-15 22:40 ` Conor Dooley
2022-09-20 12:17 ` Geert Uytterhoeven
2022-09-20 12:31 ` Conor Dooley
2022-09-20 13:46 ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-15 21:56 ` Conor.Dooley
2022-09-15 22:41 ` Lad, Prabhakar
2022-09-15 22:44 ` Conor.Dooley
2022-09-15 22:51 ` Lad, Prabhakar
2022-09-20 12:32 ` Geert Uytterhoeven
2022-09-20 14:05 ` Lad, Prabhakar
2022-09-20 15:07 ` Geert Uytterhoeven
2022-09-20 16:05 ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-20 12:34 ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=3693a3a1-5a2a-4cc5-fb55-f6ad9a4b3f72@microchip.com \
--to=conor.dooley@microchip.com \
--cc=aou@eecs.berkeley.edu \
--cc=atishp@rivosinc.com \
--cc=biju.das.jz@bp.renesas.com \
--cc=devicetree@vger.kernel.org \
--cc=geert+renesas@glider.be \
--cc=heiko@sntech.de \
--cc=krzysztof.kozlowski+dt@linaro.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-renesas-soc@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=palmer@dabbelt.com \
--cc=paul.walmsley@sifive.com \
--cc=prabhakar.csengg@gmail.com \
--cc=prabhakar.mahadev-lad.rj@bp.renesas.com \
--cc=robh+dt@kernel.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®