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From: <Conor.Dooley@microchip.com>
To: <prabhakar.csengg@gmail.com>
Cc: <geert+renesas@glider.be>, <robh+dt@kernel.org>,
	<krzysztof.kozlowski+dt@linaro.org>, <paul.walmsley@sifive.com>,
	<palmer@dabbelt.com>, <aou@eecs.berkeley.edu>, <heiko@sntech.de>,
	<atishp@rivosinc.com>, <devicetree@vger.kernel.org>,
	<linux-riscv@lists.infradead.org>,
	<linux-renesas-soc@vger.kernel.org>,
	<linux-kernel@vger.kernel.org>, <biju.das.jz@bp.renesas.com>,
	<prabhakar.mahadev-lad.rj@bp.renesas.com>
Subject: Re: [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option
Date: Thu, 15 Sep 2022 22:25:25 +0000	[thread overview]
Message-ID: <5815ce38-93f2-f6e4-2529-d6927d41ae16@microchip.com> (raw)
In-Reply-To: <CA+V-a8sv9sFwGktxqkWohQF2FfxyQm=Z5GVNjPW9i2hKxtNWpg@mail.gmail.com>



On 15/09/2022 23:18, Lad, Prabhakar wrote:
> Hi Conor,
> 
> Thank you for the review.
> 
> On Thu, Sep 15, 2022 at 9:59 PM <Conor.Dooley@microchip.com> wrote:
>>
>> On 15/09/2022 19:15, Prabhakar wrote:
>>> EXTERNAL EMAIL: Do not click links or open attachments unless you know the content is safe
>>>
>>> From: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>>
>>> Introduce SOC_RENESAS_RZFIVE config option to enable Renesas RZ/Five
>>> (R9A07G043) SoC, along side also add ARCH_RENESAS config option as most
>>> of the Renesas drivers depend on this config option.
>>>
>>> Signed-off-by: Lad Prabhakar <prabhakar.mahadev-lad.rj@bp.renesas.com>
>>> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>>> ---
>>> v2->v3
>>> * Included RB tag from Geert
>>>
>>> v1->v2
>>> * No Change
>>> ---
>>>  arch/riscv/Kconfig.socs | 14 ++++++++++++++
>>>  1 file changed, 14 insertions(+)
>>>
>>> diff --git a/arch/riscv/Kconfig.socs b/arch/riscv/Kconfig.socs
>>> index 69774bb362d6..91b7f38b77a8 100644
>>> --- a/arch/riscv/Kconfig.socs
>>> +++ b/arch/riscv/Kconfig.socs
>>> @@ -80,4 +80,18 @@ config SOC_CANAAN_K210_DTB_SOURCE
>>>
>>>  endif # SOC_CANAAN
>>>
>>> +config ARCH_RENESAS
>>> +       bool
>>> +       select GPIOLIB
>>> +       select PINCTRL
>>> +       select SOC_BUS
>>
>> Do you really need to select SOC_BUS?
>> Noone else does on RISC-V, hence my curiosity.
>>
> Yes we do need SOC_BUS due to soc_device_register() call in [0].
> Digging further I realized we can drop the above SOC_BUS as
> SOC_RENESAS is selecting SOC_BUS [1]
> 
> [0] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/renesas/renesas-soc.c?h=v6.0-rc5#n487
> [1] https://git.kernel.org/pub/scm/linux/kernel/git/torvalds/linux.git/tree/drivers/soc/renesas/Kconfig?h=v6.0-rc5#n5
> 
>>> +
>>> +config SOC_RENESAS_RZFIVE
>>> +       bool "Renesas RZ/Five SoC"
>>> +       select ARCH_R9A07G043
>>> +       select ARCH_RENESAS
>>> +       select RESET_CONTROLLER
>>> +       help
>>> +         This enables support for Renesas RZ/Five SoC.
>>
>> :thinking: isn't this pretty much what we decided not to do?
>> And instead you would redefine ARCH_RENESAS in this file and
>> not use SOC_RENESAS* at all? Will save me having to purge the
>> the SOC symbol when I do the conversion.
>>
> I was under the impression we didn't come to a conclusion so kept the

Might've been a good idea if I did a summary as I finished..
I guess I'll post one to the list tomorrow if I remember.

> patch as is. I'll just make ARCH_RENESAS visible as Geert suggested
> something like below:
> 
>         config ARCH_RENESAS
>             bool "Renesas RISC-V SoCs"
>             select GPIOLIB
>             select PINCTRL
>             select RESET_CONTROLLER
> 
> 
> Cheers,
> Prabhakar

  reply	other threads:[~2022-09-15 22:25 UTC|newest]

Thread overview: 33+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-09-15 18:15 [PATCH v3 00/10] Add support for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 01/10] dt-bindings: soc: renesas: Move renesas.yaml from arm to soc Prabhakar
2022-09-15 21:13   ` Conor.Dooley
2022-09-15 21:56     ` Lad, Prabhakar
2022-09-20 12:00   ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 02/10] dt-bindings: riscv: Sort the CPU core list alphabetically Prabhakar
2022-09-15 20:53   ` Heiko Stuebner
2022-09-15 18:15 ` [PATCH v3 03/10] dt-bindings: riscv: Add Andes AX45MP core to the list Prabhakar
2022-09-15 18:15 ` [PATCH v3 04/10] dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 05/10] RISC-V: Kconfig.socs: Add Renesas RZ/Five SoC kconfig option Prabhakar
2022-09-15 20:58   ` Conor.Dooley
2022-09-15 22:18     ` Lad, Prabhakar
2022-09-15 22:25       ` Conor.Dooley [this message]
2022-09-15 18:15 ` [PATCH v3 06/10] riscv: dts: renesas: Add initial devicetree for Renesas RZ/Five SoC Prabhakar
2022-09-15 18:15 ` [PATCH v3 07/10] riscv: boot: dts: r9a07g043: Add placeholder nodes Prabhakar
2022-09-15 21:36   ` Conor.Dooley
2022-09-15 22:26     ` Lad, Prabhakar
2022-09-15 22:40       ` Conor Dooley
2022-09-20 12:17         ` Geert Uytterhoeven
2022-09-20 12:31           ` Conor Dooley
2022-09-20 13:46             ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 08/10] riscv: dts: renesas: Add minimal DTS for Renesas RZ/Five SMARC EVK Prabhakar
2022-09-15 21:56   ` Conor.Dooley
2022-09-15 22:41     ` Lad, Prabhakar
2022-09-15 22:44       ` Conor.Dooley
2022-09-15 22:51         ` Lad, Prabhakar
2022-09-20 12:32   ` Geert Uytterhoeven
2022-09-20 14:05     ` Lad, Prabhakar
2022-09-20 15:07       ` Geert Uytterhoeven
2022-09-20 16:05         ` Lad, Prabhakar
2022-09-15 18:15 ` [PATCH v3 09/10] MAINTAINERS: Add entry for Renesas RISC-V architecture Prabhakar
2022-09-20 12:34   ` Geert Uytterhoeven
2022-09-15 18:15 ` [PATCH v3 10/10] RISC-V: configs: defconfig: Enable Renesas RZ/Five SoC Prabhakar

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