From: Nikolay Borisov <nik.borisov@suse.com>
To: Yazen Ghannam <yazen.ghannam@amd.com>,
x86@kernel.org, Tony Luck <tony.luck@intel.com>,
"Rafael J. Wysocki" <rafael@kernel.org>,
Len Brown <lenb@kernel.org>
Cc: linux-kernel@vger.kernel.org, linux-edac@vger.kernel.org,
Smita.KoralahalliChannabasappa@amd.com,
Qiuxu Zhuo <qiuxu.zhuo@intel.com>,
linux-acpi@vger.kernel.org
Subject: Re: [PATCH v4 02/22] x86/mce: Restore poll settings after storm subsides
Date: Wed, 25 Jun 2025 16:22:56 +0300 [thread overview]
Message-ID: <38243641-6aea-4d85-aeea-310c849f1043@suse.com> (raw)
In-Reply-To: <20250624-wip-mca-updates-v4-2-236dd74f645f@amd.com>
On 6/24/25 17:15, Yazen Ghannam wrote:
> Users can disable MCA polling by setting the "ignore_ce" parameter or by
> setting "check_interval=0". This tells the kernel to *not* start the MCE
> timer on a CPU.
>
> If the user did not disable CMCI, then storms can occur. When these
> happen, the MCE timer will be started with a fixed interval. After the
> storm subsides, the timer's next interval is set to check_interval.
I think the subject of the patch doesn't do justice to the patch
content. In fact, what this change does is ensure the timer function
honors CE handling being disabled either via ignore_ce or check_interval
being 0 when a CMCI storm subsides. So a subject along the lines of:
"Ensure user settings are considered when CMCI storm subsides" or
something like that is more descriptive of what you are doing.
At the very least you are not restoring anything, because even without
this patch when the storm subsided you'd start the timer with a value of
'iv'.
>
> This disregards the user's input through "ignore_ce" and
> "check_interval". Furthermore, if "check_interval=0", then the new timer
> will run faster than expected.
>
> Create a new helper to check these conditions and use it when a CMCI
> storm ends.
>
> Fixes: 7eae17c4add5 ("x86/mce: Add per-bank CMCI storm mitigation")
> Signed-off-by: Yazen Ghannam <yazen.ghannam@amd.com>
> Cc: stable@vger.kernel.org
> ---
>
> Notes:
> Link:
> https://lore.kernel.org/r/20250415-wip-mca-updates-v3-17-8ffd9eb4aa56@amd.com
>
> v3->v4:
> * Update commit message.
> * Move to beginning of set.
> * Note: Polling vs thresholding use case updates not yet addressed.
>
> v2->v3:
> * New in v3.
>
> arch/x86/kernel/cpu/mce/core.c | 9 +++++++--
> 1 file changed, 7 insertions(+), 2 deletions(-)
>
> diff --git a/arch/x86/kernel/cpu/mce/core.c b/arch/x86/kernel/cpu/mce/core.c
> index 07d61937427f..ae2e2d8ec99b 100644
> --- a/arch/x86/kernel/cpu/mce/core.c
> +++ b/arch/x86/kernel/cpu/mce/core.c
> @@ -1740,6 +1740,11 @@ static void mc_poll_banks_default(void)
>
> void (*mc_poll_banks)(void) = mc_poll_banks_default;
>
> +static bool should_enable_timer(unsigned long iv)
> +{
> + return !mca_cfg.ignore_ce && iv;
> +}
> +
> static void mce_timer_fn(struct timer_list *t)
> {
> struct timer_list *cpu_t = this_cpu_ptr(&mce_timer);
> @@ -1763,7 +1768,7 @@ static void mce_timer_fn(struct timer_list *t)
>
> if (mce_get_storm_mode()) {
> __start_timer(t, HZ);
> - } else {
> + } else if (should_enable_timer(iv)) {
> __this_cpu_write(mce_next_interval, iv);
> __start_timer(t, iv);
> }
> @@ -2156,7 +2161,7 @@ static void mce_start_timer(struct timer_list *t)
> {
> unsigned long iv = check_interval * HZ;
>
> - if (mca_cfg.ignore_ce || !iv)
> + if (!should_enable_timer(iv))
> return;
>
> this_cpu_write(mce_next_interval, iv);
>
next prev parent reply other threads:[~2025-06-25 13:22 UTC|newest]
Thread overview: 42+ messages / expand[flat|nested] mbox.gz Atom feed top
2025-06-24 14:15 [PATCH v4 00/22] AMD MCA interrupts rework Yazen Ghannam
2025-06-24 14:15 ` [PATCH v4 01/22] x86/mce: Don't remove sysfs if thresholding sysfs init fails Yazen Ghannam
2025-06-28 11:33 ` [tip: ras/urgent] " tip-bot2 for Yazen Ghannam
2025-06-24 14:15 ` [PATCH v4 02/22] x86/mce: Restore poll settings after storm subsides Yazen Ghannam
2025-06-25 13:22 ` Nikolay Borisov [this message]
2025-06-28 11:33 ` [tip: ras/urgent] x86/mce: Ensure user polling settings are honored when restarting timer tip-bot2 for Yazen Ghannam
2025-06-24 14:15 ` [PATCH v4 03/22] x86/mce/amd: Add default names for MCA banks and blocks Yazen Ghannam
2025-06-28 11:33 ` [tip: ras/urgent] " tip-bot2 for Yazen Ghannam
2025-06-24 14:15 ` [PATCH v4 04/22] x86/mce/amd: Fix threshold limit reset Yazen Ghannam
2025-06-28 11:33 ` [tip: ras/urgent] " tip-bot2 for Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 05/22] x86/mce/amd: Rename threshold restart function Yazen Ghannam
2025-09-05 11:40 ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 06/22] x86/mce/amd: Remove return value for mce_threshold_{create,remove}_device() Yazen Ghannam
2025-06-25 14:57 ` Nikolay Borisov
2025-09-05 11:40 ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 07/22] x86/mce/amd: Remove smca_banks_map Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 08/22] x86/mce/amd: Put list_head in threshold_bank Yazen Ghannam
2025-06-25 16:52 ` Nikolay Borisov
2025-06-27 11:14 ` Nikolay Borisov
2025-06-30 12:57 ` Yazen Ghannam
2025-08-25 13:59 ` Borislav Petkov
2025-09-05 11:40 ` [tip: ras/core] " tip-bot2 for Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 09/22] x86/mce: Cleanup bank processing on init Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 10/22] x86/mce: Remove __mcheck_cpu_init_early() Yazen Ghannam
2025-06-26 8:03 ` Nikolay Borisov
2025-06-30 12:58 ` Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 11/22] x86/mce: Define BSP-only init Yazen Ghannam
2025-06-25 11:04 ` Nikolay Borisov
2025-06-25 11:26 ` Borislav Petkov
2025-06-24 14:16 ` [PATCH v4 12/22] x86/mce: Define BSP-only SMCA init Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 13/22] x86/mce: Do 'UNKNOWN' vendor check early Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 14/22] x86/mce: Separate global and per-CPU quirks Yazen Ghannam
2025-06-27 11:02 ` Nikolay Borisov
2025-06-30 13:00 ` Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 15/22] x86/mce: Move machine_check_poll() status checks to helper functions Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 16/22] x86/mce: Unify AMD THR handler with MCA Polling Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 17/22] x86/mce: Unify AMD DFR " Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 18/22] x86/mce/amd: Support SMCA Corrected Error Interrupt Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 19/22] x86/mce/amd: Remove redundant reset_block() Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 20/22] x86/mce/amd: Define threshold restart function for banks Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 21/22] x86/mce: Handle AMD threshold interrupt storms Yazen Ghannam
2025-06-24 14:16 ` [PATCH v4 22/22] x86/mce: Save and use APEI corrected threshold limit Yazen Ghannam
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