* [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards
@ 2025-09-04 7:40 Gatien Chevallier
2025-09-04 7:40 ` [PATCH v2 1/4] arm64: dts: st: add eth1 pins for stm32mp2x platforms Gatien Chevallier
` (4 more replies)
0 siblings, 5 replies; 6+ messages in thread
From: Gatien Chevallier @ 2025-09-04 7:40 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin,
Alexandre Torgue
Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel,
Gatien Chevallier
All of the current stm32mp2x boards embed an ethernet1 SNPS GMAC5.x
controller.
Add the support for it on stm32mp235f-dk, stm32mp257f-dk and
stm32mp257f-ev1 boards and default enable it.
On the stm32mp257f-ev1 board, we choose to keep the ethernet1
controller as a standalone ethernet controller instead of using
the TSN capable switch.
Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com>
---
Changes in v2:
- Remove pointless max-speed properties
- Fix property ordering (reg after compatible) in the stm32mp257f-ev1
- Link to v1: https://lore.kernel.org/r/20250903-mp2_ethernet-v1-0-4105b0ad2344@foss.st.com
---
Gatien Chevallier (4):
arm64: dts: st: add eth1 pins for stm32mp2x platforms
arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk
arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1
arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk
arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 23 +++++
arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 126 ++++++++++++++++++++++++++
arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 23 +++++
arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 +++++
4 files changed, 196 insertions(+)
---
base-commit: 08a5d1b176ed503a5cef40991fc89549d85e8fe8
change-id: 20250902-mp2_ethernet-97ddde08f903
Best regards,
--
Gatien Chevallier <gatien.chevallier@foss.st.com>
^ permalink raw reply [flat|nested] 6+ messages in thread* [PATCH v2 1/4] arm64: dts: st: add eth1 pins for stm32mp2x platforms 2025-09-04 7:40 [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Gatien Chevallier @ 2025-09-04 7:40 ` Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 2/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk Gatien Chevallier ` (3 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Gatien Chevallier @ 2025-09-04 7:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Gatien Chevallier Eth1 ethernet controller is present on every stm32mp2x vendor boards. Describe the pinctrl of eth1 for each of them. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 126 ++++++++++++++++++++++++++ 1 file changed, 126 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi index 5ac9e72478dddb82be0ef7432d7e728932b2f4d6..3a2a82de48536ef4fe625b69a61e91f746b0d53f 100644 --- a/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi +++ b/arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi @@ -6,6 +6,132 @@ #include <dt-bindings/pinctrl/stm32-pinfunc.h> &pinctrl { + eth1_mdio_pins_a: eth1-mdio-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, AF10)>; /* ETH_MDC */ + bias-disable; + drive-push-pull; + slew-rate = <2>; + }; + pins2 { + pinmux = <STM32_PINMUX('F', 2, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <0>; + }; + }; + + eth1_mdio_sleep_pins_a: eth1-mdio-sleep-0 { + pins1 { + pinmux = <STM32_PINMUX('F', 0, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('F', 2, ANALOG)>; /* ETH_MDIO */ + }; + }; + + eth1_rgmii_pins_a: eth1-rgmii-0 { + pins1 { + pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, AF12)>; /* ETH_RGMII_GTX_CLK */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_a: eth1-rgmii-sleep-0 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('A', 14, ANALOG)>; /* ETH_RGMII_RX_CLK */ + }; + }; + + eth1_rgmii_pins_b: eth1-rgmii-1 { + pins1 { + pinmux = <STM32_PINMUX('A', 15, AF10)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, AF10)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, AF10)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, AF10)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, AF10)>; /* ETH_RGMII_TX_CTL */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins2 { + pinmux = <STM32_PINMUX('H', 9, AF10)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, AF12)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 9, AF10)>, /* ETH_MDC */ + <STM32_PINMUX('A', 10, AF10)>; /* ETH_MDIO */ + bias-disable; + drive-push-pull; + slew-rate = <3>; + }; + pins3 { + pinmux = <STM32_PINMUX('F', 1, AF10)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, AF10)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, AF10)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, AF10)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, AF10)>; /* ETH_RGMII_RX_CTL */ + bias-disable; + }; + pins4 { + pinmux = <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + bias-disable; + }; + }; + + eth1_rgmii_sleep_pins_b: eth1-rgmii-sleep-1 { + pins { + pinmux = <STM32_PINMUX('A', 15, ANALOG)>, /* ETH_RGMII_TXD0 */ + <STM32_PINMUX('C', 1, ANALOG)>, /* ETH_RGMII_TXD1 */ + <STM32_PINMUX('H', 10, ANALOG)>, /* ETH_RGMII_TXD2 */ + <STM32_PINMUX('H', 11, ANALOG)>, /* ETH_RGMII_TXD3 */ + <STM32_PINMUX('A', 13, ANALOG)>, /* ETH_RGMII_TX_CTL */ + <STM32_PINMUX('H', 9, ANALOG)>, /* ETH_RGMII_CLK125 */ + <STM32_PINMUX('C', 0, ANALOG)>, /* ETH_RGMII_GTX_CLK */ + <STM32_PINMUX('A', 9, ANALOG)>, /* ETH_MDC */ + <STM32_PINMUX('A', 10, ANALOG)>, /* ETH_MDIO */ + <STM32_PINMUX('F', 1, ANALOG)>, /* ETH_RGMII_RXD0 */ + <STM32_PINMUX('C', 2, ANALOG)>, /* ETH_RGMII_RXD1 */ + <STM32_PINMUX('H', 12, ANALOG)>, /* ETH_RGMII_RXD2 */ + <STM32_PINMUX('H', 13, ANALOG)>, /* ETH_RGMII_RXD3 */ + <STM32_PINMUX('A', 11, ANALOG)>, /* ETH_RGMII_RX_CTL */ + <STM32_PINMUX('A', 14, AF10)>; /* ETH_RGMII_RX_CLK */ + }; + }; + eth2_rgmii_pins_a: eth2-rgmii-0 { pins1 { pinmux = <STM32_PINMUX('C', 7, AF10)>, /* ETH_RGMII_TXD0 */ -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 2/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk 2025-09-04 7:40 [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 1/4] arm64: dts: st: add eth1 pins for stm32mp2x platforms Gatien Chevallier @ 2025-09-04 7:40 ` Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 3/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 Gatien Chevallier ` (2 subsequent siblings) 4 siblings, 0 replies; 6+ messages in thread From: Gatien Chevallier @ 2025-09-04 7:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Gatien Chevallier ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp257f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts index a278a1e3ce03aa379d40ef807d268bbf31a04546..e718d888ce21b6f124331543c09c1e66e6304964 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-dk.dts @@ -19,6 +19,7 @@ / { compatible = "st,stm32mp257f-dk", "st,stm32mp257"; aliases { + ethernet0 = ðernet1; serial0 = &usart2; }; @@ -77,6 +78,28 @@ &arm_wdt { status = "okay"; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 3/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 2025-09-04 7:40 [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 1/4] arm64: dts: st: add eth1 pins for stm32mp2x platforms Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 2/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk Gatien Chevallier @ 2025-09-04 7:40 ` Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 4/4] arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk Gatien Chevallier 2025-09-15 15:35 ` [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Alexandre TORGUE 4 siblings, 0 replies; 6+ messages in thread From: Gatien Chevallier @ 2025-09-04 7:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Gatien Chevallier ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. It can either be used as a standalone Ethernet controller or be connected to the internal TSN capable switch. For this board, keep the standalone setup. Also enable this peripheral on the stm32mp257f-ev1 board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts index 4ff334563599b46e987474076798337e75e16ef7..1135826c011ef40c3b16ac5cd888ede85e54165d 100644 --- a/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts +++ b/arch/arm64/boot/dts/st/stm32mp257f-ev1.dts @@ -19,6 +19,7 @@ / { aliases { ethernet0 = ðernet2; + ethernet1 = ðernet1; serial0 = &usart2; serial1 = &usart6; }; @@ -133,6 +134,29 @@ dcmipp_0: endpoint { }; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_a ð1_mdio_pins_a>; + pinctrl-1 = <ð1_rgmii_sleep_pins_a ð1_mdio_sleep_pins_a>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + st,ext-phyclk; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@4 { + compatible = "ethernet-phy-id001c.c916"; + reg = <4>; + reset-gpios = <&gpioj 9 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + ðernet2 { pinctrl-names = "default", "sleep"; pinctrl-0 = <ð2_rgmii_pins_a>; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* [PATCH v2 4/4] arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk 2025-09-04 7:40 [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Gatien Chevallier ` (2 preceding siblings ...) 2025-09-04 7:40 ` [PATCH v2 3/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 Gatien Chevallier @ 2025-09-04 7:40 ` Gatien Chevallier 2025-09-15 15:35 ` [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Alexandre TORGUE 4 siblings, 0 replies; 6+ messages in thread From: Gatien Chevallier @ 2025-09-04 7:40 UTC (permalink / raw) To: Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin, Alexandre Torgue Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel, Gatien Chevallier ethernet1 controller is connected to the RTL8211F-CG Realtek PHY in RGMII mode. Enable this peripheral on the stm32mp235f-dk board. Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> --- arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 23 +++++++++++++++++++++++ 1 file changed, 23 insertions(+) diff --git a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts index 04d1b434c433e5f76d120f4bd254c15a2de3fb94..29ccf8dab35e85fac15ae64f46c65c296b0fb22a 100644 --- a/arch/arm64/boot/dts/st/stm32mp235f-dk.dts +++ b/arch/arm64/boot/dts/st/stm32mp235f-dk.dts @@ -19,6 +19,7 @@ / { compatible = "st,stm32mp235f-dk", "st,stm32mp235"; aliases { + ethernet0 = ðernet1; serial0 = &usart2; }; @@ -77,6 +78,28 @@ &arm_wdt { status = "okay"; }; +ðernet1 { + pinctrl-0 = <ð1_rgmii_pins_b>; + pinctrl-1 = <ð1_rgmii_sleep_pins_b>; + pinctrl-names = "default", "sleep"; + phy-handle = <&phy1_eth1>; + phy-mode = "rgmii-id"; + status = "okay"; + + mdio { + #address-cells = <1>; + #size-cells = <0>; + compatible = "snps,dwmac-mdio"; + phy1_eth1: ethernet-phy@1 { + compatible = "ethernet-phy-id001c.c916"; + reg = <1>; + reset-gpios = <&gpioa 2 GPIO_ACTIVE_LOW>; + reset-assert-us = <10000>; + reset-deassert-us = <80000>; + }; + }; +}; + &scmi_regu { scmi_vddio1: regulator@0 { regulator-min-microvolt = <1800000>; -- 2.25.1 ^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards 2025-09-04 7:40 [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Gatien Chevallier ` (3 preceding siblings ...) 2025-09-04 7:40 ` [PATCH v2 4/4] arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk Gatien Chevallier @ 2025-09-15 15:35 ` Alexandre TORGUE 4 siblings, 0 replies; 6+ messages in thread From: Alexandre TORGUE @ 2025-09-15 15:35 UTC (permalink / raw) To: Gatien Chevallier, Rob Herring, Krzysztof Kozlowski, Conor Dooley, Maxime Coquelin Cc: devicetree, linux-stm32, linux-arm-kernel, linux-kernel Hi Gatien On 9/4/25 09:40, Gatien Chevallier wrote: > All of the current stm32mp2x boards embed an ethernet1 SNPS GMAC5.x > controller. > > Add the support for it on stm32mp235f-dk, stm32mp257f-dk and > stm32mp257f-ev1 boards and default enable it. > > On the stm32mp257f-ev1 board, we choose to keep the ethernet1 > controller as a standalone ethernet controller instead of using > the TSN capable switch. > > Signed-off-by: Gatien Chevallier <gatien.chevallier@foss.st.com> > --- > Changes in v2: > - Remove pointless max-speed properties > - Fix property ordering (reg after compatible) in the stm32mp257f-ev1 > - Link to v1: https://lore.kernel.org/r/20250903-mp2_ethernet-v1-0-4105b0ad2344@foss.st.com > > --- > Gatien Chevallier (4): > arm64: dts: st: add eth1 pins for stm32mp2x platforms > arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk > arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 > arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk > > arch/arm64/boot/dts/st/stm32mp235f-dk.dts | 23 +++++ > arch/arm64/boot/dts/st/stm32mp25-pinctrl.dtsi | 126 ++++++++++++++++++++++++++ > arch/arm64/boot/dts/st/stm32mp257f-dk.dts | 23 +++++ > arch/arm64/boot/dts/st/stm32mp257f-ev1.dts | 24 +++++ > 4 files changed, 196 insertions(+) > --- > base-commit: 08a5d1b176ed503a5cef40991fc89549d85e8fe8 > change-id: 20250902-mp2_ethernet-97ddde08f903 > > Best regards, Series applied on stm32-next. Thanks!! Alex ^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2025-09-15 15:36 UTC | newest] Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2025-09-04 7:40 [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 1/4] arm64: dts: st: add eth1 pins for stm32mp2x platforms Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 2/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-dk Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 3/4] arm64: dts: st: enable ethernet1 controller on stm32mp257f-ev1 Gatien Chevallier 2025-09-04 7:40 ` [PATCH v2 4/4] arm64: dts: st: enable ethernet1 controller on stm32mp235f-dk Gatien Chevallier 2025-09-15 15:35 ` [PATCH v2 0/4] arm64: dts: st: add ethernet1 controller support on stm32mp23/25 boards Alexandre TORGUE
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®